An Approximate Method For Calculation Of Fluid Force And Response Of A Circular Cylinder At Lock-In

In this paper, equations calculating lift force of a rigid circular cyclinder at lock-in uniform flow are deduced in detail. Besides, equations calculating the lift force on a long flexible circular cyclinder at lock-in are deduced based on mode analysis of a multi-degree freedom system. The simplified forms of these equations are also given. Furthermore, an approximate method to predict the forces and response of rigid circular cyclinders and long flexible circular cyclinders at lock-in is introduced in the case of low mass-damping ratio. A method to eliminate one deficiency of these equations is introduced. Comparison with experimental results show the effectiveness of this approximate method.

High-Strength Composite Fibers: Realizing True Potential of Carbon Nanotubes in Polymer Matrix through Continuous Reticulate Architecture and Molecular Level Couplings

Carbon nanotubes have unprecedented mechanical properties as defect-free nanoscale building blocks, but their potential has not been fully realized in composite materials due to weakness at the interfaces. Here we demonstrate that through load-transfer-favored three-dimensional architecture and molecular level couplings with polymer chains, true potential of CNTs can be realized in composites as Initially envisioned. Composite fibers with reticulate nanotube architectures show order of magnitude improvement in strength compared to randomly dispersed short CNT reinforced composites reported before. The molecular level couplings between nanotubes and polymer chains results in drastic differences in the properties of thermoset and thermoplastic composite fibers, which indicate that conventional macroscopic composite theory falls to explain the overall hybrid behavior at nanoscale.

Comparative mechanisms of photosynthetic carbon acquisition in Hizikia fusiforme under submersed and emersed conditions

The economic seaweed Hizikia fusiforme (Harv.) Okamura (Sargassaceae, Phaeophyta) usually experiences periodical exposures to air at low tide. Photosynthetic carbon acquisition mechanisms were comparatively studied under submersed and emersed conditions in order to establish a general understanding of its photosynthetic characteristics associated with tidal cycles. When submersed in seawater, H fusiforme was capable of acquiring HCO3- as a source of inorganic carbon (Ci) to drive photosynthesis, while emersed and exposed to air, it used atmospheric CO2 for photosynthesis. The pH changes surrounding the H fusiforme fronds had less influence on the photosynthetic rates under emersed condition than under submersed condition. When the pH was as high as 10.0, emersed H fusiforme could photosynthesize efficiently, but the submersed alga exhibited very poor photosynthesis. Extracellular carbonic anhydrase (CA) played an important role in the photosynthetic acquisitions of exogenous Ci in water as well as in air. Both the concentrations of dissolved inorganic carbon in general seawater and CO2 in air were demonstrated to limit the photosynthesis of H fusiforme, which was sensitive to O-2. It appeared that the exogenous carbon acquisition system, being dependent of external CA activity, operates in a way not enough to raise intracellular CO2 level to prevent photorespiration. The inability of H fusiforme to achieve its maximum photosynthetic rate at the current ambient Ci levels under both submersed and emersed conditions suggested that the yield of aquaculture for this economic species would respond profitably to future increases in CO2 concentration in the sea and air.

CONTRIBUTION OF BACTERIOPLANKTON, PHYTOPLANKTON, ZOOPLANKTON AND DETRITUS TO ORGANIC SESTON CARBON LOAD IN A CHANGJIANG FLOODPLAIN LAKE (CHINA)

The relative compositions of bacterioplankton, phytoplankton, zooplankton and detritus of seston were studied during the course of inundation in a floodplain lake of central Changjiang (China). Peaks in bacterial biomass developed shortly after flooding, coinciding with the initial leaching of organic nutrients from vegetation submerged under floodwater, and again at high water, shortly before the climax of phytoplankton biomass. Rods predominated the bacterial carbon biomass. Phytoplankton developed a postflood bloom at initial falling, corresponding to the drainage of the lake water into the river. While minimal biomass occurred during the advent of flooding, most likely due to disturbance and dilution. Algal biomass was usually dominated by Chlorophyta. Highest biomass of zooplankton was recorded at the end of the flooding in connection with the decline in turbidity, and once again at early drainage, closely associated with high phytoplankton biomass. Copepods (mainly nauplii) always constituted the majority of zooplankton carbon biomass. Peaks in detrital carbon concentrations were recorded at rising and falling water phases, corresponding respectively to the riverine discharge and decomposition of macrophyte mats. At rising water phase, CPOC was abundant. While during other water phases, this predominance was shifted to FPOC alone. Taken together, average contribution of bacterioplankton, phytoplankton, zooplankton and detritus to total seston carbon was 3.29, 21.21, 6.83 and 68.67 %, respectively.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.