适合于小飞机防撞系统的机载小型激光测距仪

报道了一种重量轻、功耗低、适合于小飞机防撞系统应用的小型激光测距仪。系统基于脉冲激光测距原理，采用905nm半导体脉冲激光器、电感升压式偏置高压电源和可编程逻辑器件（PLD），研制出重量不大于100g，功耗不大于625mW，测量范围100m，盲区3．0m，分辨率±1m的机载小型激光测距仪。实验测试结果表明，其各项技术性能指标符合无人驾驶小飞机防撞系统的应用要求。

WIA建筑能耗测量与优化运行系统

在分析建筑高能耗原因的基础上,提出了一个基于WIA的建筑能耗测量与优化运行方案,详细介绍了该方案的结构组成和原理。

基于工业无线网络WIA技术的储油罐监测系统

在分析现有的储油罐区监测技术的基础上,提出了一个基于工业无线网络WIA技术的储油罐监测系统方案,详细介绍了该方案的系统运行原理、系统结构及系统功能。

基于工业无线网络WIA技术的管道泄漏监测系统

在分析现有的管道泄漏监测技术的基础上,提出了一个基于工业无线网络WIA技术的管道泄漏监测系统方案,详细介绍了该方案的系统运行原理、系统结构及系统性能及特点。

基于以太网的工业控制网络

应用传统现场总线的工业控制网络无法实现办公室自动化与工业自动化的无缝结合 .由于以太网在确定性、速度和优先法则等方面性能的提高 ,阻碍以太网应用于实时控制环境的难点已被解决 .以太网早已成为商业管理网络的首要选择 ,那么它应用于企业现场设备控制层是控制网络发展的趋势 ,将极大地促进信息从传感器到管理层的集成

automated test program generation for an industrial optimizing compiler

Association for Computing Machinery, ACM; IEEE; IEEE Computer Society; SIGSOFT

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Effects of Thermocapillary Convection on the Growth Process in Industrial 8-inch Silicon Czochralski Growth

Czochralski (CZ) crystal growth process is a widely used technique in manufacturing of silicon crystals and other semiconductor materials. The ultimate goal of the IC industry is to have the highest quality substrates, which are free of point defect, impurities and micro defect clusters. The scale up of silicon wafer size from 200 mm to 300 mm requires large crucible size and more heat power. Transport phenomena in crystal growth processes are quite complex due to melt and gas flows that may be oscillatory and/or turbulent, coupled convection and radiation, impurities and dopant distributions, unsteady kinetics of the growth process, melt crystal interface dynamics, free surface and meniscus, stoichiometry in the case of compound materials. A global model has been developed to simulate the temperature distribution and melt flow in an 8-inch system. The present program features the fluid convection, magnetohydrodynamics, and radiation models. A multi-zone method is used to divide the Cz system into different zones, e.g., the melt, the crystal and the hot zone. For calculation of temperature distribution, the whole system inside the stainless chamber is considered. For the convective flow, only the melt is considered. The widely used zonal method divides the surface of the radiation enclosure into a number of zones, which has a uniform distribution of temperature, radiative properties and composition. The integro-differential equations for the radiative heat transfer are solved using the matrix inversion technique. The zonal method for radiative heat transfer is used in the growth chamber, which is confined by crystal surface, melt surface, heat shield, and pull chamber. Free surface and crystal/melt interface are tracked using adaptive grid generation. The competition between the thermocapillary convection induced by non-uniform temperature distributions on the free surface and the forced convection by the rotation of the crystal determines the interface shape, dopant distribution, and striation pattern. The temperature gradients on the free surface are influenced by the effects of the thermocapillary force on the free surface and the rotation of the crystal and the crucible.

Pulse compression by filamentation in argon with an acoustic optical programmable dispersive filter for predispersion compensation

We have experimentally demonstrated pulses 0.4 mJ in duration smaller than 12 fs; with an excellent spatial beam profile by self-guided propagation in argon. The original 52 fs pulses from the chirped pulsed amplification laser system are first precompressed to 32 fs by inserting an acoustic optical programmable dispersive filter instrument into the laser system for spectrum reshaping and dispersion compensation, and the pulse spectrum is subsequently broadened by filamentation in an argon cell. By using chirped mirrors for post-dispersion compensation, the pulses are successfully compressed to smaller than 12 fs.

Parallel optical negabinary arithmetic based on logic operations

On the basis of signed-digit negabinary representation, parallel two-step addition and one-step subtraction can be performed for arbitrary-length negabinary operands.; The arithmetic is realized by signed logic operations and optically implemented by spatial encoding and decoding techniques. The proposed algorithm and optical system are simple, reliable, and practicable, and they have the property of parallel processing of two-dimensional data. This leads to an efficient design for the optical arithmetic and logic unit. (C) 1997 Optical Society of America.

Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio. (C) 1999 Optical Society of America.

Logic-operated mathematical morphology and its optical implementation

A more powerful tool for binary image processing, i.e., logic-operated mathematical morphology (LOMM), is proposed. With LOMM the image and the structuring element (SE) are treated as binary logical variables, and the MULTIPLY between the image and the SE in correlation is replaced with 16 logical operations. A total of 12 LOMM operations are obtained. The optical implementation of LOMM is described. The application of LOMM and its experimental results are also presented. (C) 1999 Optical Society of America.

Code conversion from signed-digit to complement representation based on look-ahead optical logic operations

We present, for the first time to our knowledge, a generalized lookahead logic algorithm for number conversion from signed-digit to complement representation. By properly encoding the signed-digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quarternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using an electron-trapping device is employed and experimental results are shown. This optical module is suitable for implementing complex logic functions in the form of the sum of the product. The algorithm and architecture are compatible with a general-purpose optoelectronic computing system. (C) 2001 Society of Photo-Optical Instrumentation Engineers.