62 resultados para silicon wafer

em Universidad Politécnica de Madrid


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In the Laser-Fired Contact (LFC) process, a laser beam fires a metallic layer through a dielectric passivating layer into the silicon wafer to form an electrical contact with the silicon bulk [1]. This laser technique is an interesting alternative for the fabrication of both laboratory and industrial scale high efficiency passivated emitter and rear cell (PERC). One of the principal characteristics of this promising technique is the capability to reduce the recombination losses at the rear surface in crystalline silicon solar cells. Therefore, it is crucial to optimize LFC because this process is one of the most promising concepts to produce rear side point contacts at process speeds compatible with the final industrial application. In that sense, this work investigates the optimization of LFC processing to improve the back contact in silicon solar cells using fully commercial solid state lasers with pulse width in the ns range, thus studying the influence of the wavelength using the three first harmonics (corresponding to wavelengths of 1064 nm, 532 nm and 355 nm). Previous studies of our group focused their attention in other processing parameters as laser fluence, number of pulses, passivating material [2, 3] thickness of the rear metallic contact [4], etc. In addition, the present work completes the parametric optimization by assessing the influence of the laser wavelength on the contact property. In particular we report results on the morphology and electrical behaviour of samples specifically designed to assess the quality of the process. In order to study the influence of the laser wavelength on the contact feature we used as figure of merit the specific contact resistance. In all processes the best results have been obtained using green (532 nm) and UV (355 nm), with excellent values for this magnitude far below 1 mΩcm2.

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In this work we propose a method for cleaving silicon-based photonic chips by using a laser based micromachining system, consisting of a ND:YVO4laser emitting at 355 nm in nanosecond pulse regime and a micropositioning system. The laser makes grooved marks placed at the desired locations and directions where cleaves have to be initiated, and after several processing steps, a crack appears and propagate along the crystallographic planes of the silicon wafer. This allows cleavage of the chips automatically and with high positioning accuracy, and provides polished vertical facets with better quality than the obtained with other cleaving process, which eases the optical characterization of photonic devices. This method has been found to be particularly useful when cleaving small-sized chips, where manual cleaving is hard to perform; and also for polymeric waveguides, whose facets get damaged or even destroyed with polishing or manual cleaving processing. Influence of length of the grooved line and speed of processing is studied for a variety of silicon chips. An application for cleaving and characterizing sol–gel waveguides is presented. The total amount of light coupled is higher than when using any other procedure.

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The dissolution and gettering of iron is studied during the final fabrication step of multicrystalline silicon solar cells, the co-firing step, through simulations and experiments. The post-processed interstitial iron concentration is simulated according to the as-grown concentration and distribution of iron within a silicon wafer, both in the presence and absence of the phosphorus emitter, and applying different time-temperature profiles for the firing step. The competing effects of dissolution and gettering during the short annealing process are found to be strongly dependant on the as-grown material quality. Furthermore, increasing the temperature of the firing process leads to a higher dissolution of iron, hardly compensated by the higher diffusivity of impurities. A new defect engineering tool is introduced, the extended co-firing, which could allow an enhanced gettering effect within a small additional time

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As wafer-based solar cells become thinner, light-trapping textures for absorption enhancement will gain in importance. In this work, crystalline silicon wafers were textured with wavelength-scale diffraction grating surface textures by nanoimprint lithography using interference lithography as a mastering technology. This technique allows fine-tailored nanostructures to be realized on large areas with high throughput. Solar cell precursors were fabricated, with the surface textures on the rear side, for optical absorption measurements. Large absorption enhancements are observed in the wavelength range in which the silicon wafer absorbs weakly. It is shown experimentally that bi-periodic crossed gratings perform better than uni-periodic linear gratings. Optical simulations have been made of the fabricated structures, allowing the total absorption to be decomposed into useful absorption in the silicon and parasitic absorption in the rear reflector. Using the calculated silicon absorption, promising absorbed photocurrent density enhancements have been calculated for solar cells employing the nano-textures. Finally, first results are presented of a passivation layer deposition technique that planarizes the rear reflector for the purpose of reducing the parasitic absorption.

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This article presents a wide band compact high isolation photoconductive switch, which is based on the series-shunt switch design with three photoconductive switches made of diced high-resistivity silicon wafer placed over a microstrip gap and activated by 808-nm near-infrared laser diodes. The switch shows an insertion loss of 1.2 dB and an isolation of 44.8 dB at 2 GHz. It is easy to operate and control by light, high-speed, electromagnetically transparent and it does not require any biasing circuits.

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The highest solar cell efficiencies both for c-Si and mc-Si were reached using template based texturing processes. Especially for mc-Si the benefit of a defined texture, the so called honeycomb texture, was demonstrated impressively. However, up until now, no industrially feasible process has been available to pattern the necessary etching masks with the sufficient resolution. Roller-Nanoimprint Lithography (Roller-NIL) has the potential to overcome these limitations and to allow high quality pattern transfers, even in the sub-micron regime, in continuous in-line processes. Therefore, this etch-mask patterning technique is a suitable solution to bring such elaborate features like the honeycomb texture to an industrial realization. Beyond that, this fast printing-like technology opens up new possibilities to introduce promising concepts like photonic structures into solar cells.

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The era of the seed-cast grown monocrystalline-based silicon ingots is coming. Mono-like, pseudomono or quasimono wafers are product labels that can be nowadays found in the market, as a critical innovation for the photovoltaic industry. They integrate some of the most favorable features of the conventional silicon substrates for solar cells, so far, such as the high solar cell efficiency offered by the monocrystalline Czochralski-Si (Cz-Si) wafers and the lower cost, high productivity and full square-shape that characterize the well-known multicrystalline casting growth method. Nevertheless, this innovative crystal growth approach still faces a number of mass scale problems that need to be resolved, in order to gain a deep, 100% reliable and worldwide market: (i) extended defects formation during the growth process; (ii) optimization of the seed recycling; and (iii) parts of the ingots giving low solar cells performance, which directly affect the production costs and yield of this approach. Therefore, this paper presents a series of casting crystal growth experiments and characterization studies from ingots, wafers and cells manufactured in an industrial approach, showing the main sources of crystal defect formation, impurity enrichment and potential consequences at solar cell level. The previously mentioned technological drawbacks are directly addressed, proposing industrial actions to pave the way of this new wafer technology to high efficiency solar cells.

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Silicon wafers comprise approximately 40% of crystalline silicon module cost, and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled to effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. To accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.

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The objective of the present study is the estimation of the depth to which the wire sawing process causes damage to the wafer surfaces. Previous analyses were carried out by means of the four line bending test. The characteristic of this test implied that the failure could be due to surface cracks located in the central zone of the wafer or near the edges. In order to evaluate the influence of the edge or surface cracks a new study has been carried out using the ball/ring on ring test. Description and results of the tests are presented. The preliminary analysis of the failure stress using analytical methods confirms the expected results. A Finite Element model developed to get more information of the test results is also presented.

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A phosphorus diffusion gettering model is used to examine the efficacy of a standard gettering process on interstitial and precipitated iron in multicrystalline silicon. The model predicts a large concentration of precipitated iron remaining after standard gettering for most as-grown iron distributions. Although changes in the precipitated iron distribution are predicted to be small, the simulated post-processing interstitial iron concentration is predicted to depend strongly on the as-grown distribution of precipitates, indicating that precipitates must be considered as internal sources of contamination during processing. To inform and validate the model, the iron distributions before and after a standard phosphorus diffusion step are studied in samples from the bottom, middle, and top of an intentionally Fe-contaminated laboratory ingot. A census of iron-silicide precipitates taken by synchrotron-based X-ray fluorescence microscopy confirms the presence of a high density of iron-silicide precipitates both before and after phosphorus diffusion. A comparable precipitated iron distribution was measured in a sister wafer after hydrogenation during a firing step. The similar distributions of precipitated iron seen after each step in the solar cell process confirm that the effect of standard gettering on precipitated iron is strongly limited as predicted by simulation. Good agreement between the experimental and simulated data supports the hypothesis that gettering kinetics is governed by not only the total iron concentration but also by the distribution of precipitated iron. Finally, future directions based on the modeling are suggested for the improvement of effective minority carrier lifetime in multicrystalline silicon solar cells.

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Dual-junction solar cells formed by a GaAsP or GaInP top cell and a silicon bottom cell seem to be attractive candidates to materialize the long sought-for integration of III-V materials on silicon for photovoltaic applications. One of the first issues to be considered in the development of this structure will be the strategy to create the silicon emitter of the bottom subcell. In this study, we explore the possibility of forming the silicon emitter by phosphorus diffusion (i.e. exposing the wafer to PH3 in a MOVPE reactor) and still obtain good surface morphologies to achieve a successful III-V heteroepitaxy as occurs in conventional III-V on germanium solar cell technology. Consequently, we explore the parameter space (PH3 partial pressure, time and temperature) that is needed to create optimized emitter designs and assess the impact of such treatments on surface morphology using atomic force microscopy. Although a strong degradation of surface morphology caused by prolonged exposure of silicon to PH3 is corroborated, it is also shown that subsequent anneals under H-2 can recover silicon surface morphology and minimize its RMS roughness and the presence of pits and spikes.

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With the final goal of integrating III-V materials on silicon substrates for tandem solar cells, the influence of the Metal-Organic Vapor Phase Epitaxy (MOVPE) environment on the minority carrier properties of silicon wafers has been evaluated. These properties will essentially determine the photovoltaic performance of the bottom cell in a III-V-on-Si tandem solar cell. A comparison of the base minority carrier lifetimes obtained for different thermal processes carried out in a MOVPE reactor on Czochralski silicon wafers has been carried out. An important degradation of minority carrier lifetime during the surface preparation (i.e. H2 anneal) has been observed. Three different mechanisms have been proposed for explaining this behavior: 1) the introduction of extrinsic impurities coming from the reactor; 2) the activation of intrinsic lifetime killing impurities coming from the wafer itself; and finally, 3) the formation of crystal defects, which eventually become recombination centers. The effect of the emitter formation by phosphorus diffusion has also been evaluated. In this sense, it has been reported that lifetime can be recovered during the emitter formation either by the effect of the P on extracting impurities, or by the role of the atomic hydrogen on passivating the defects.

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The work presented here aims to reduce the cost of multijunction solar cell technology by developing ways to manufacture them on cheap substrates such as silicon. In particular, our main objective is the growth of III-V semiconductors on silicon substrates for photovoltaic applications. The goal is to create a GaAsP/Si virtual substrates onto which other III-V cells could be integrated with an interesting efficiency potential. This technology involves several challenges due to the difficulty of growing III-V materials on silicon. In this paper, our first work done aimed at developing such structure is presented. It was focused on the development of phosphorus diffusion models on silicon and on the preparation of an optimal silicon surface to grow on it III-V materials.

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Founded by Antonio Luque in 1979 Personnel: Personnel: 6464 full full-time time staff (19 professors staff (19 professors, 44 PhD PhD researchers 28 PhD students 13 researchers, 28 PhD students, 13 administrative and maintenance staff), 19 “part time” (11 “external PhD students”, 8 master students) Objective: Objective: Contribute to the deployment of Photovoltaic Solar Electricity through R&D& Contribute to the deployment of Photovoltaic Solar Electricity through R&D&i

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The introduction of a low-temperature (LT) tail after P emitter diffusion was shown to lead to considerable improvements in electron lifetime and solar cell performance by different researchers. So far, the drawback of the investigated extended gettering treatments has been the lack of knowledge about optimum annealing times and temperatures and the important increase in processing time. In this manuscript, we calculate optimum annealing temperatures of Fe-contaminated Si wafers for different annealing durations. Subsequently, it is shown theoretically and experimentally that a relatively short LT tail of 15 min can lead to a significant reduction of interstitial Fe and an increase in electron lifetime. Finally, we calculate the potential improvement of solar cell efficiency when such a short-tail extended P diffusion gettering is included in an industrial fabrication process.