Individualization and Electrical Characterization of SiGe Nanowires

SiGe nanowires of different Ge atomic fractions up to 15% were grown and ex-situ n-type doped by diffusion from a solid source in contact with the sample. The phenomenon of dielectrophoresis was used to locate single nanowires between pairs of electrodes in order to carry out electrical measurements. The measured resistance of the as-grown nanowires is very high, but it decreases more than three orders of magnitude upon doping, indicating that the doping procedure used has been effective

SiGe nanowires grown by LPCVD using Ga-Au catalysts

The use of Ga-Au alloys as metal catalysts for the growth of SiGe nanowires has been investigated. The grown nanowires are cylindrical and straight, with a defect-free crystalline structure, sharp nanowire-droplet interfaces and an almost constant Ge atomic fraction throughout all their length. These features represent significant improvements over the results obtained using pure Au

SiGe/Si nanowire axial heterostructures grown by LPCVD using Ga-Au

The use of Ga-Au alloys of different compositions as metal catalysts for the growth of abrupt SiGe/Si nanowire axial heterostructures has been investigated. The heterostructures grown in a continuous process by just switching the gas precursors, show uniform nanowire diameters, almost abrupt compositional changes and no defects between the different sections. These features represent significant improvements over the results obtained using pure Au.

Si and SixGe1-x NWs studied by Raman spectroscopy

Group IV nanostructures have attracted a great deal of attention because of their potential applications in optoelectronics and nanodevices. Raman spectroscopy has been extensively used to characterize nanostructures since it provides non destructive information about their size, by the adequate modeling of the phonon confinement effect. The Raman spectrum is also sensitive to other factors, as stress and temperature, which can mix with the size effects borrowing the interpretation of the Raman spectrum. We present herein an analysis of the Raman spectra obtained for Si and SiGe nanowires; the influence of the excitation conditions and the heat dissipation media are discussed in order to optimize the experimental conditions for reliable spectra acquisition and interpretation.

Raman spectroscopy in Group IV nanowires and nanowire axial heterostructures

The control of the SiGe NW composition is fundamental for the fabrication of high quality heterostructures. Raman spectroscopy has been used to analyse the composition of SiGe alloys. We present a study of the Raman spectrum of SiGe nanowires and SiGe/Si heterostructures. The inhomogeneity of the Ge composition deduced from the Raman spectrum is explained by the existence of a Ge-rich outer shell and by the interaction of the NW with the electromagnetic field associated with the laser beam.

Design and Simulation of Deep Nanometer SRAM Cells under Energy, Mismatch, and Radiation Constraints

La fiabilidad está pasando a ser el principal problema de los circuitos integrados según la tecnología desciende por debajo de los 22nm. Pequeñas imperfecciones en la fabricación de los dispositivos dan lugar ahora a importantes diferencias aleatorias en sus características eléctricas, que han de ser tenidas en cuenta durante la fase de diseño. Los nuevos procesos y materiales requeridos para la fabricación de dispositivos de dimensiones tan reducidas están dando lugar a diferentes efectos que resultan finalmente en un incremento del consumo estático, o una mayor vulnerabilidad frente a radiación. Las memorias SRAM son ya la parte más vulnerable de un sistema electrónico, no solo por representar más de la mitad del área de los SoCs y microprocesadores actuales, sino también porque las variaciones de proceso les afectan de forma crítica, donde el fallo de una única célula afecta a la memoria entera. Esta tesis aborda los diferentes retos que presenta el diseño de memorias SRAM en las tecnologías más pequeñas. En un escenario de aumento de la variabilidad, se consideran problemas como el consumo de energía, el diseño teniendo en cuenta efectos de la tecnología a bajo nivel o el endurecimiento frente a radiación. En primer lugar, dado el aumento de la variabilidad de los dispositivos pertenecientes a los nodos tecnológicos más pequeños, así como a la aparición de nuevas fuentes de variabilidad por la inclusión de nuevos dispositivos y la reducción de sus dimensiones, la precisión del modelado de dicha variabilidad es crucial. Se propone en la tesis extender el método de inyectores, que modela la variabilidad a nivel de circuito, abstrayendo sus causas físicas, añadiendo dos nuevas fuentes para modelar la pendiente sub-umbral y el DIBL, de creciente importancia en la tecnología FinFET. Los dos nuevos inyectores propuestos incrementan la exactitud de figuras de mérito a diferentes niveles de abstracción del diseño electrónico: a nivel de transistor, de puerta y de circuito. El error cuadrático medio al simular métricas de estabilidad y prestaciones de células SRAM se reduce un mínimo de 1,5 veces y hasta un máximo de 7,5 a la vez que la estimación de la probabilidad de fallo se mejora en varios ordenes de magnitud. El diseño para bajo consumo es una de las principales aplicaciones actuales dada la creciente importancia de los dispositivos móviles dependientes de baterías. Es igualmente necesario debido a las importantes densidades de potencia en los sistemas actuales, con el fin de reducir su disipación térmica y sus consecuencias en cuanto al envejecimiento. El método tradicional de reducir la tensión de alimentación para reducir el consumo es problemático en el caso de las memorias SRAM dado el creciente impacto de la variabilidad a bajas tensiones. Se propone el diseño de una célula que usa valores negativos en la bit-line para reducir los fallos de escritura según se reduce la tensión de alimentación principal. A pesar de usar una segunda fuente de alimentación para la tensión negativa en la bit-line, el diseño propuesto consigue reducir el consumo hasta en un 20 % comparado con una célula convencional. Una nueva métrica, el hold trip point se ha propuesto para prevenir nuevos tipos de fallo debidos al uso de tensiones negativas, así como un método alternativo para estimar la velocidad de lectura, reduciendo el número de simulaciones necesarias. Según continúa la reducción del tamaño de los dispositivos electrónicos, se incluyen nuevos mecanismos que permiten facilitar el proceso de fabricación, o alcanzar las prestaciones requeridas para cada nueva generación tecnológica. Se puede citar como ejemplo el estrés compresivo o extensivo aplicado a los fins en tecnologías FinFET, que altera la movilidad de los transistores fabricados a partir de dichos fins. Los efectos de estos mecanismos dependen mucho del layout, la posición de unos transistores afecta a los transistores colindantes y pudiendo ser el efecto diferente en diferentes tipos de transistores. Se propone el uso de una célula SRAM complementaria que utiliza dispositivos pMOS en los transistores de paso, así reduciendo la longitud de los fins de los transistores nMOS y alargando los de los pMOS, extendiéndolos a las células vecinas y hasta los límites de la matriz de células. Considerando los efectos del STI y estresores de SiGe, el diseño propuesto mejora los dos tipos de transistores, mejorando las prestaciones de la célula SRAM complementaria en más de un 10% para una misma probabilidad de fallo y un mismo consumo estático, sin que se requiera aumentar el área. Finalmente, la radiación ha sido un problema recurrente en la electrónica para aplicaciones espaciales, pero la reducción de las corrientes y tensiones de los dispositivos actuales los está volviendo vulnerables al ruido generado por radiación, incluso a nivel de suelo. Pese a que tecnologías como SOI o FinFET reducen la cantidad de energía colectada por el circuito durante el impacto de una partícula, las importantes variaciones de proceso en los nodos más pequeños va a afectar su inmunidad frente a la radiación. Se demuestra que los errores inducidos por radiación pueden aumentar hasta en un 40 % en el nodo de 7nm cuando se consideran las variaciones de proceso, comparado con el caso nominal. Este incremento es de una magnitud mayor que la mejora obtenida mediante el diseño de células de memoria específicamente endurecidas frente a radiación, sugiriendo que la reducción de la variabilidad representaría una mayor mejora. ABSTRACT Reliability is becoming the main concern on integrated circuit as the technology goes beyond 22nm. Small imperfections in the device manufacturing result now in important random differences of the devices at electrical level which must be dealt with during the design. New processes and materials, required to allow the fabrication of the extremely short devices, are making new effects appear resulting ultimately on increased static power consumption, or higher vulnerability to radiation SRAMs have become the most vulnerable part of electronic systems, not only they account for more than half of the chip area of nowadays SoCs and microprocessors, but they are critical as soon as different variation sources are regarded, with failures in a single cell making the whole memory fail. This thesis addresses the different challenges that SRAM design has in the smallest technologies. In a common scenario of increasing variability, issues like energy consumption, design aware of the technology and radiation hardening are considered. First, given the increasing magnitude of device variability in the smallest nodes, as well as new sources of variability appearing as a consequence of new devices and shortened lengths, an accurate modeling of the variability is crucial. We propose to extend the injectors method that models variability at circuit level, abstracting its physical sources, to better model sub-threshold slope and drain induced barrier lowering that are gaining importance in FinFET technology. The two new proposed injectors bring an increased accuracy of figures of merit at different abstraction levels of electronic design, at transistor, gate and circuit levels. The mean square error estimating performance and stability metrics of SRAM cells is reduced by at least 1.5 and up to 7.5 while the yield estimation is improved by orders of magnitude. Low power design is a major constraint given the high-growing market of mobile devices that run on battery. It is also relevant because of the increased power densities of nowadays systems, in order to reduce the thermal dissipation and its impact on aging. The traditional approach of reducing the voltage to lower the energy consumption if challenging in the case of SRAMs given the increased impact of process variations at low voltage supplies. We propose a cell design that makes use of negative bit-line write-assist to overcome write failures as the main supply voltage is lowered. Despite using a second power source for the negative bit-line, the design achieves an energy reduction up to 20% compared to a conventional cell. A new metric, the hold trip point has been introduced to deal with new sources of failures to cells using a negative bit-line voltage, as well as an alternative method to estimate cell speed, requiring less simulations. With the continuous reduction of device sizes, new mechanisms need to be included to ease the fabrication process and to meet the performance targets of the successive nodes. As example we can consider the compressive or tensile strains included in FinFET technology, that alter the mobility of the transistors made out of the concerned fins. The effects of these mechanisms are very dependent on the layout, with transistor being affected by their neighbors, and different types of transistors being affected in a different way. We propose to use complementary SRAM cells with pMOS pass-gates in order to reduce the fin length of nMOS devices and achieve long uncut fins for the pMOS devices when the cell is included in its corresponding array. Once Shallow Trench isolation and SiGe stressors are considered the proposed design improves both kinds of transistor, boosting the performance of complementary SRAM cells by more than 10% for a same failure probability and static power consumption, with no area overhead. While radiation has been a traditional concern in space electronics, the small currents and voltages used in the latest nodes are making them more vulnerable to radiation-induced transient noise, even at ground level. Even if SOI or FinFET technologies reduce the amount of energy transferred from the striking particle to the circuit, the important process variation that the smallest nodes will present will affect their radiation hardening capabilities. We demonstrate that process variations can increase the radiation-induced error rate by up to 40% in the 7nm node compared to the nominal case. This increase is higher than the improvement achieved by radiation-hardened cells suggesting that the reduction of process variations would bring a higher improvement.

Is Microarray Analysis Really Useful and Sufficient to Diagnose Nut Allergy in the Mediterranean Area?

Background: Component-based diagnosis on multiplex platforms is widely used in food allergy but its clinical performance has not been evaluated in nut allergy. Objective: To assess the diagnostic performance of a commercial protein microarray in the determination of specific IgE (sIgE) in peanut, hazelnut, and walnut allergy. Methods: sIgE was measured in 36 peanut-allergic, 36 hazelnut-allergic, and 44 walnut-allergic patients by ISAC 112, and subsequently, sIgE against available components was determined by ImmunoCAP in patients with negative ISAC results. ImmunoCAP was also used to measure sIgE to Ara h 9, Cor a 8, and Jug r 3 in a subgroup of lipid transfer protein (LTP)-sensitized nut-allergic patients (positive skin prick test to LTP-enriched extract). sIgE levels by ImmunoCAP were compared with ISAC ranges. Results: Most peanut-, hazelnut-, and walnut-allergic patients were sensitized to the corresponding nut LTP (Ara h 9, 66.7%; Cor a 8, 80.5%; Jug r 3, 84% respectively). However, ISAC did not detect sIgE in 33.3% of peanut-allergic patients, 13.9% of hazelnut-allergic patients, or 13.6% of walnut-allergic patients. sIgE determination by ImmunoCAP detected sensitization to Ara h 9, Cor a 8, and Jug r 3 in, respectively, 61.5% of peanut-allergic patients, 60% of hazelnut-allergic patients, and 88.3% of walnut-allergic patients with negative ISAC results. In the subgroup of peach LTP?sensitized patients, Ara h 9 sIgE was detected in more cases by ImmunoCAP than by ISAC (94.4% vs 72.2%, P<.05). Similar rates of Cor a 8 and Jug r 3 sensitization were detected by both techniques. Conclusions: The diagnostic performance of ISAC was adequate for hazelnut and walnut allergy but not for peanut allergy. sIgE sensitivity against Ara h 9 in ISAC needs to be improved.

Is the performance of ImmunoCAP ISAC 112 sufficient to diagnose peach and apple allergies?

Food allergies constitute a public health issue, with a reported overall estimated prevalence of 6% in Europe1 and Rosacea as the main allergenic fruits among adults.2 The commercial microarray ImmunoCAP ISAC 112 (Thermofisher, Uppsala, Sweden) is a semiquantitative and reproducible in vitro diagnostic tool used for the determination of specific IgE (sIgE).3 However, its panel of allergens does not have the best accuracy when it comes to determining fruit allergies in the Mediterranean area: the inclusion of the thaumatinlike protein (TLP) Pru p 2 or the apple lipid transfer protein (LTP) Mal d 3 has been proposed to improve the diagnosis of peach4 and apple5 allergies, respectively, in the Mediterranean basin. We sought to determine the usefulness of a component-resolved microarray for the diagnosis of peach and apple allergies in the Mediterranean area.