169 resultados para Static CMOS logic gates


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Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

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En este proyecto, se presenta un sensor de temperatura integrado CMOS basado en la medida de una variable secundaria, cuyo valor es dependiente de la temperatura, como es el tiempo de subida que presenta una señal eléctrica en sus flancos de subida. Con el objetivo de reducir coste y potencia consumida, el sensor integrado de temperatura propuesto genera un pulso con un ancho proporcional a la temperatura medida. Este sensor para realizar la medida elimina la necesidad de tener una señal que sirva de referencia. El área ocupada por este modelo de sensor es de 1.8967mm2, siendo éste fabricado en tecnología CMOS de 0.35µm de 4 capas de metal. Gracias a la excelente linealidad que presenta la salida digital del sensor, el error de medida alcanzado es como máximo de ±0.520ºC. La resolución efectiva mostrada en el caso peor es de 0.7ºC, y el consumo de potencia se encuentra por debajo de los 263µW, con una velocidad de realización de medidas que puede llegar a alcanzar las 1.5x10^6 medidas por segundo.

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After more than a decade of development work and hopes, the usage of mobile Internet has finally taken off. Now, we are witnessing the first signs of evidence of what might become the explosion of mobile content and applications that will be shaping the (mobile) Internet of the future. Similar to the wired Internet, search will become very relevant for the usage of mobile Internet. Current research on mobile search has applied a limited set of methodologies and has also generated a narrow outcome of meaningful results. This article covers new ground, exploring the use and visions of mobile search with a users' interview-based qualitative study. Its main conclusion builds upon the hypothesis that mobile search is sensitive to a mobile logic different than today's one. First, (advanced) users ask for accessing with their mobile devices the entire Internet, rather than subsections of it. Second, success is based on new added-value applications that exploit unique mobile functionalities. The authors interpret that such mobile logic involves fundamentally the use of personalised and context-based services.

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La norma UNE-EN 13374 “Sistemas provisionales de protección de borde. Especificaciones del producto, métodos de ensayo” (1) clasifica los sistemas provisionales de protección de borde (SPPB) en tres clases (A, B y C), en función del ángulo de la superficie de trabajo y de la altura de caída de la persona a proteger. Los sistemas clase A son los indicados cuando la inclinación de la superficie de trabajo es menor de 10º. La norma establece los requisitos de flecha y de resistencia de los SPPB. Los requisitos se pueden comprobar tanto analítica como experimentalmente. El objetivo del trabajo ha sido la evaluación del comportamiento de los SPPB utilizados habitualmente en las obras y establecer los cambios necesarios para que cumplan con la norma UNE-EN 13374. Para ello se han evaluado analítica y experimentalmente tres SPPB clase A, fabricados con acero S235. Los resultados obtenidos muestran que, el sistema empleado de forma habitual en obras no supera los requisitos de la norma ni analítica ni experimentalmente. El tercer sistema supera los requisitos con las dos metodologías de análisis. El segundo sistema supera los requisitos cuando la evaluación se realiza analíticamente pero no cuando la vía utilizada es la experimental.

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In this paper, a new countermeasure against power and electromagnetic (EM) Side Channel Attacks (SCA) on FPGA implemented cryptographic algorithms is proposed. This structure mainly focuses on a critical vulnerability, Early Evaluation, also known as Early Propagation Effect (EPE), which exists in most conventional SCA-hardened DPL (Dual-rail with Precharge Logic) solutions. The main merit of this proposal is that the EPE can be effectively prevented by using a synchronized non regular precharge network, which maintains identical routing between the original and mirror parts, where costs and design complexity compared with previous EPE-resistant countermeasures are reduced, while security level is not sacrificed. Another advantage for our Precharge Absorbed(PA) - DPL method is that its Dual-Core style (independent architecture for true and false parts) could be generated using partial reconfiguration. This helps to get a dynamic security protection with better energy planning. That means system only keeps the true part which fulfills the normal en/decryption task in low security level, and reconfigures the false parts once high security level is required. A relatively limited clock speed is a compromise, since signal propagation is restricted to a portion of the clock period. In this paper, we explain the principles of PA-DPL and provide the guidelines to design this structure. We experimentally validate our methods in a minimized AES co-processor on Xilinx Virtex-5 board using electromagnetic (EM) attacks.

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Publicación de la Sede del Consejo Consultor de Castilla y León en Zamora en la revista de arquitectura IA&B (Mumbai). El proyecto de Zamora se centra en el diálogo entre una pieza cristina de vidrio y el grueso muro de piedra perimetral. Estas dos fachadas entran en relación gracias a un patio perimetral que tensa el contacto entre entre el vidrio y la piedra. Se hace especial mención de la estricta precisión y racionalidad del proyecto. La publicación contiene textos, dibujos planimétricos, fotografías y materiales del proceso de investigación en el proyecto (croquis y fotografías de maquetas).

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El cálculo de relaciones binarias fue creado por De Morgan en 1860 para ser posteriormente desarrollado en gran medida por Peirce y Schröder. Tarski, Givant, Freyd y Scedrov demostraron que las álgebras relacionales son capaces de formalizar la lógica de primer orden, la lógica de orden superior así como la teoría de conjuntos. A partir de los resultados matemáticos de Tarski y Freyd, esta tesis desarrolla semánticas denotacionales y operacionales para la programación lógica con restricciones usando el álgebra relacional como base. La idea principal es la utilización del concepto de semántica ejecutable, semánticas cuya característica principal es el que la ejecución es posible utilizando el razonamiento estándar del universo semántico, este caso, razonamiento ecuacional. En el caso de este trabajo, se muestra que las álgebras relacionales distributivas con un operador de punto fijo capturan toda la teoría y metateoría estándar de la programación lógica con restricciones incluyendo los árboles utilizados en la búsqueda de demostraciones. La mayor parte de técnicas de optimización de programas, evaluación parcial e interpretación abstracta pueden ser llevadas a cabo utilizando las semánticas aquí presentadas. La demostración de la corrección de la implementación resulta extremadamente sencilla. En la primera parte de la tesis, un programa lógico con restricciones es traducido a un conjunto de términos relacionales. La interpretación estándar en la teoría de conjuntos de dichas relaciones coincide con la semántica estándar para CLP. Las consultas contra el programa traducido son llevadas a cabo mediante la reescritura de relaciones. Para concluir la primera parte, se demuestra la corrección y equivalencia operacional de esta nueva semántica, así como se define un algoritmo de unificación mediante la reescritura de relaciones. La segunda parte de la tesis desarrolla una semántica para la programación lógica con restricciones usando la teoría de alegorías—versión categórica del álgebra de relaciones—de Freyd. Para ello, se definen dos nuevos conceptos de Categoría Regular de Lawvere y _-Alegoría, en las cuales es posible interpretar un programa lógico. La ventaja fundamental que el enfoque categórico aporta es la definición de una máquina categórica que mejora e sistema de reescritura presentado en la primera parte. Gracias al uso de relaciones tabulares, la máquina modela la ejecución eficiente sin salir de un marco estrictamente formal. Utilizando la reescritura de diagramas, se define un algoritmo para el cálculo de pullbacks en Categorías Regulares de Lawvere. Los dominios de las tabulaciones aportan información sobre la utilización de memoria y variable libres, mientras que el estado compartido queda capturado por los diagramas. La especificación de la máquina induce la derivación formal de un juego de instrucciones eficiente. El marco categórico aporta otras importantes ventajas, como la posibilidad de incorporar tipos de datos algebraicos, funciones y otras extensiones a Prolog, a la vez que se conserva el carácter 100% declarativo de nuestra semántica. ABSTRACT The calculus of binary relations was introduced by De Morgan in 1860, to be greatly developed by Peirce and Schröder, as well as many others in the twentieth century. Using different formulations of relational structures, Tarski, Givant, Freyd, and Scedrov have shown how relation algebras can provide a variable-free way of formalizing first order logic, higher order logic and set theory, among other formal systems. Building on those mathematical results, we develop denotational and operational semantics for Constraint Logic Programming using relation algebra. The idea of executable semantics plays a fundamental role in this work, both as a philosophical and technical foundation. We call a semantics executable when program execution can be carried out using the regular theory and tools that define the semantic universe. Throughout this work, the use of pure algebraic reasoning is the basis of denotational and operational results, eliminating all the classical non-equational meta-theory associated to traditional semantics for Logic Programming. All algebraic reasoning, including execution, is performed in an algebraic way, to the point we could state that the denotational semantics of a CLP program is directly executable. Techniques like optimization, partial evaluation and abstract interpretation find a natural place in our algebraic models. Other properties, like correctness of the implementation or program transformation are easy to check, as they are carried out using instances of the general equational theory. In the first part of the work, we translate Constraint Logic Programs to binary relations in a modified version of the distributive relation algebras used by Tarski. Execution is carried out by a rewriting system. We prove adequacy and operational equivalence of the semantics. In the second part of the work, the relation algebraic approach is improved by using allegory theory, a categorical version of the algebra of relations developed by Freyd and Scedrov. The use of allegories lifts the semantics to typed relations, which capture the number of logical variables used by a predicate or program state in a declarative way. A logic program is interpreted in a _-allegory, which is in turn generated from a new notion of Regular Lawvere Category. As in the untyped case, program translation coincides with program interpretation. Thus, we develop a categorical machine directly from the semantics. The machine is based on relation composition, with a pullback calculation algorithm at its core. The algorithm is defined with the help of a notion of diagram rewriting. In this operational interpretation, types represent information about memory allocation and the execution mechanism is more efficient, thanks to the faithful representation of shared state by categorical projections. We finish the work by illustrating how the categorical semantics allows the incorporation into Prolog of constructs typical of Functional Programming, like abstract data types, and strict and lazy functions.

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Plate-bandes are straight masonry arches (they are called, also, flat arches or lintel arches). Ideally they have the surfaces of extrados and intrados plane and horizontal. The stones or bricks have radial joints converging usually in one centre. The voussoirs have the form of wedges and in French they are called "claveaux". A plate-bande is, in fact, a lintel made of several stones and the proportions of lintels and plate-bandes are similar. Proportions of plate-bandes, that is the relationship between the thickness t and the span s (t/s)varies, typically between 1/4–1/3 in thick plate-bandes, and is less than 1/20 in the most slender ones. A ratio of circa 1/8 was usual in the 18th Century and follows a simple geometrical rule: the centre form with the intrados an equilateral triangle and the plate-bande should contain an arc of circle. The joints are usually plane, but in some cases present a «rebated» or «stepped» form. Plate-bandes exert an inclined thrust as any masonry arch. This thrust is usually very high and it requires either massive buttresses, or to be built in the middle of thick walls. Master builders and architects have tried since antiquity to calculate the abutment necessary for any arch. A modern architect or engineer will measure the arch thrust in units of force, kN or tons. Traditionally, the thrust has been measured as the size of the buttresses to resist it safely. Old structural rules, then, addressed the design problem establishing a relationship between the span and the depth of the buttress. These were empirical rules, particular for every type of arch or structure in every epoch. Thus, the typical gothic buttress is 1/4 of the vault span, but a Renaissance or baroque barrel vault will need more than 1/3 of the span. A plate-bande would require more than one half of the span; this is precisely the rule cited by the French engineer Gautier, who tried unsuccessfully to justify it by static reasons. They were used, typically, to form the lintels of windows or doors (1-2 m, typically); in Antiquity they were used, also, though rarely, at the gates of city walls or in niches (ca. 2 m, reaching 5.2 m). Plate-bandes may show particular problems: it is not unusual that some sliding of the voussoirs can be observed, particularly in thick plate-bandes. The stepped joints on Fig. 1, left, were used to avoid this problem. There are other «hidden» methods, like iron cramps or the use of stone wedges, etc. In seismic zones these devices were usual. Another problem relates to the deformation; a slight yielding of the abutments, or even the compression of the mortar joints, may lead to some cracking and the descent of the central keystone. Even a tiny descent will convert the original straight line of the intrados in a broken line with a visible «kink» or angle in the middle. Of course, both problems should be avoided. Finally, the wedge form of the voussoirs lead to acute angles in the stones and this can produce partial fractures; this occurs usually at the inferior border of the springers at the abutments. It follows, that to build a successful plate-bande is not an easy matter. Also, the structural study of plate-bandes is far from simple, and mechanics and geometry are related in a particular way. In the present paper we will concentrate on the structural aspects and their constructive consequences, with a historical approach. We will outline the development of structural analysis of plate-bandes from ca. 1700 until today. This brief history has a more than purely academic interest. Different approaches and theories pointed to particular problem, and though the solution given may have been incorrect, the question posed was often pertinent. The paper ends with the application of modern Limit Analysis of Masonry Structures, developed mainly by professor Heyman in the last fifty years. The work aims, also, to give some clues for the actual architect and engineer involved in the analysis or restoration of masonry buildings.

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We propose an analysis for detecting procedures and goals that are deterministic (i.e., that produce at most one solution at most once),or predicates whose clause tests are mutually exclusive (which implies that at most one of their clauses will succeed) even if they are not deterministic. The analysis takes advantage of the pruning operator in order to improve the detection of mutual exclusion and determinacy. It also supports arithmetic equations and disequations, as well as equations and disequations on terms,for which we give a complete satisfiability testing algorithm, w.r.t. available type information. Information about determinacy can be used for program debugging and optimization, resource consumption and granularity control, abstraction carrying code, etc. We have implemented the analysis and integrated it in the CiaoPP system, which also infers automatically the mode and type information that our analysis takes as input. Experiments performed on this implementation show that the analysis is fairly accurate and efficient.

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Irregular computations pose sorne of the most interesting and challenging problems in automatic parallelization. Irregularity appears in certain kinds of numerical problems and is pervasive in symbolic applications. Such computations often use dynamic data structures, which make heavy use of pointers. This complicates all the steps of a parallelizing compiler, from independence detection to task partitioning and placement. Starting in the mid 80s there has been significant progress in the development of parallelizing compilers for logic pro­gramming (and more recently, constraint programming) resulting in quite capable paralle­lizers. The typical applications of these paradigms frequently involve irregular computations, and make heavy use of dynamic data structures with pointers, since logical variables represent in practice a well-behaved form of pointers. This arguably makes the techniques used in these compilers potentially interesting. In this paper, we introduce in a tutoríal way, sorne of the problems faced by parallelizing compilers for logic and constraint programs and provide pointers to sorne of the significant progress made in the area. In particular, this work has resulted in a series of achievements in the areas of inter-procedural pointer aliasing analysis for independence detection, cost models and cost analysis, cactus-stack memory management, techniques for managing speculative and irregular computations through task granularity control and dynamic task allocation such as work-stealing schedulers), etc.

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Systems relying on fixed hardware components with a static level of parallelism can suffer from an underuse of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macroblock (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly

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Global analyzers traditionally read and analyze the entire program at once, in a nonincremental way. However, there are many situations which are not well suited to this simple model and which instead require reanalysis of certain parts of a program which has already been analyzed. In these cases, it appears inecient to perform the analysis of the program again from scratch, as needs to be done with current systems. We describe how the xed-point algorithms used in current generic analysis engines for (constraint) logic programming languages can be extended to support incremental analysis. The possible changes to a program are classied into three types: addition, deletion, and arbitrary change. For each one of these, we provide one or more algorithms for identifying the parts of the analysis that must be recomputed and for performing the actual recomputation. The potential benets and drawbacks of these algorithms are discussed. Finally, we present some experimental results obtained with an implementation of the algorithms in the PLAI generic abstract interpretation framework. The results show signicant benets when using the proposed incremental analysis algorithms.

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A stress-detection system is proposed based on physiological signals. Concretely, galvanic skin response (GSR) and heart rate (HR) are proposed to provide information on the state of mind of an individual, due to their nonintrusiveness and noninvasiveness. Furthermore, specific psychological experiments were designed to induce properly stress on individuals in order to acquire a database for training, validating, and testing the proposed system. Such system is based on fuzzy logic, and it described the behavior of an individual under stressing stimuli in terms of HR and GSR. The stress-detection accuracy obtained is 99.5% by acquiring HR and GSR during a period of 10 s, and what is more, rates over 90% of success are achieved by decreasing that acquisition period to 3-5 s. Finally, this paper comes up with a proposal that an accurate stress detection only requires two physiological signals, namely, HR and GSR, and the fact that the proposed stress-detection system is suitable for real-time applications.

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This article considers static analysis based on abstract interpretation of logic programs over combined domains. It is known that analyses over combined domains provide more information potentially than obtained by the independent analyses. However, the construction of a combined analysis often requires redefining the basic operations for the combined domain. A practical approach to maintain precision in combined analyses of logic programs which reuses the individual analyses and does not redefine the basic operations is illustrated. The advantages of the approach are that proofs of correctness for the new domains are not required and implementations can be reused. The approach is demonstrated by showing that a combined sharing analysis — constructed from "old" proposals — compares well with other "new" proposals suggested in recent literature both from the point of view of efficiency and accuracy.

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Compilation techniques such as those portrayed by the Warren Abstract Machine(WAM) have greatly improved the speed of execution of logic programs. The research presented herein is geared towards providing additional performance to logic programs through the use of parallelism, while preserving the conventional semantics of logic languages. Two áreas to which special attention is given are the preservation of sequential performance and storage efficiency, and the use of low overhead mechanisms for controlling parallel execution. Accordingly, the techniques used for supporting parallelism are efficient extensions of those which have brought high inferencing speeds to sequential implementations. At a lower level, special attention is also given to design and simulation detail and to the architectural implications of the execution model behavior. This paper offers an overview of the basic concepts and techniques used in the parallel design, simulation tools used, and some of the results obtained to date.