Oblique Angle Deposition of Germanium Film on Silicon Substrate

The effect of flux angle, substrate temperature and deposition rate on obliquely deposited germanium (Ge) films has been investigated. By carrying out deposition with the vapor flux inclined at 87° to the substrate normal at substrate temperatures of 250°C or 300°C, it may be possible to obtain isolated Ge nanowires. The Ge nanowires are crystalline as shown by Raman Spectroscopy.

Strained Silicon on Silicon by Wafer Bonding and Layer Transfer from Relaxed SiGe Buffer

We report the creation of strained silicon on silicon (SSOS) substrate technology. The method uses a relaxed SiGe buffer as a template for inducing tensile strain in a Si layer, which is then bonded to another Si handle wafer. The original Si wafer and the relaxed SiGe buffer are subsequently removed, thereby transferring a strained-Si layer directly to Si substrate without intermediate SiGe or oxide layers. Complete removal of Ge from the structure was confirmed by cross-sectional transmission electron microscopy as well as secondary ion mass spectrometry. A plan-view transmission electron microscopy study of the strained-Si/Si interface reveals that the lattice-mismatch between the layers is accommodated by an orthogonal array of edge dislocations. This misfit dislocation array, which forms upon bonding, is geometrically necessary and has an average spacing of approximately 40nm, in excellent agreement with established dislocation theory. To our knowledge, this is the first study of a chemically homogeneous, yet lattice-mismatched, interface.

Femtosecond laser processing of crystalline silicon

This paper reports the surface morphologies and ablation of crystalline silicon wafers irradiated by infra-red 775 nm Ti:sapphire femtosecond laser. The effects of energy fluences (below and above single-pulse modification) with different number of pulses were studied. New morphological features such as pits, cracks formation, Laser-Induced Periodic Surface Structures (LIPSS) and ablation were observed. The investigation indicated that there are two distinct mechanisms under femtosecond laser irradiation: low fluence regime with different morphological features and high fluence regime with high material removal and without complex morphological features.

Plasma polymerization of C[subscript 4]F[subscript 8] thin film on high aspect ratio silicon molds

High aspect ratio polymeric micro-patterns are ubiquitous in many fields ranging from sensors, actuators, optics, fluidics and medical. Second generation PDMS molds are replicated against first generation silicon molds created by deep reactive ion etching. In order to ensure successful demolding, the silicon molds are coated with a thin layer of C[subscript 4]F[subscript 8] plasma polymer to reduce the adhesion force. Peel force and demolding status are used to determine if delamination is successful. Response surface method is employed to provide insights on how changes in coil power, passivating time and gas flow conditions affect plasma polymerization of C[subscript 4]F[subscript 8].

Piezoelectric Ultrasonic Micromotors

This report describes development of micro-fabricated piezoelectric ultrasonic motors and bulk-ceramic piezoelectric ultrasonic motors. Ultrasonic motors offer the advantage of low speed, high torque operation without the need for gears. They can be made compact and lightweight and provide a holding torque in the absence of applied power, due to the traveling wave frictional coupling mechanism between the rotor and the stator. This report covers modeling, simulation, fabrication and testing of ultrasonic motors. Design of experiments methods were also utilized to find optimal motor parameters. A suite of 8 mm diameter x 3 mm tall motors were machined for these studies and maximum stall torques as large as 10^(- 3) Nm, maximum no-load speeds of 1710 rpm and peak power outputs of 27 mW were realized. Aditionally, this report describes the implementation of a microfabricated ultrasonic motor using thin-film lead zirconate titanate. In a joint project with the Pennsylvania State University Materials Research Laboratory and MIT Lincoln Laboratory, 2 mm and 5 mm diameter stator structures were fabricated on 1 micron thick silicon nitride membranes. Small glass lenses placed down on top spun at 100-300 rpm with 4 V excitation at 90 kHz. The large power densities and stall torques of these piezoelectric ultrasonic motors offer tremendous promis for integrated machines: complete intelligent, electro-mechanical autonomous systems mass-produced in a single fabrication process.

Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.