An Interpolative Analytical Cache Model with Application to Performance-Power Design Space Exploration

Caches are known to consume up to half of all system power in embedded processors. Co-optimizing performance and power of the cache subsystems is therefore an important step in the design of embedded systems, especially those employing application specific instruction processors. In this project, we propose an analytical cache model that succinctly captures the miss performance of an application over the entire cache parameter space. Unlike exhaustive trace driven simulation, our model requires that the program be simulated once so that a few key characteristics can be obtained. Using these application-dependent characteristics, the model can span the entire cache parameter space consisting of cache sizes, associativity and cache block sizes. In our unified model, we are able to cater for direct-mapped, set and fully associative instruction, data and unified caches. Validation against full trace-driven simulations shows that our model has a high degree of fidelity. Finally, we show how the model can be coupled with a power model for caches such that one can very quickly decide on pareto-optimal performance-power design points for rapid design space exploration.

A Concurrent Smalltalk Compiler for the Message-Driven Processor

This thesis describes Optimist, an optimizing compiler for the Concurrent Smalltalk language developed by the Concurrent VLSI Architecture Group. Optimist compiles Concurrent Smalltalk to the assembly language of the Message-Driven Processor (MDP). The compiler includes numerous optimization techniques such as dead code elimination, dataflow analysis, constant folding, move elimination, concurrency analysis, duplicate code merging, tail forwarding, use of register variables, as well as various MDP-specific optimizations in the code generator. The MDP presents some unique challenges and opportunities for compilation. Due to the MDP's small memory size, it is critical that the size of the generated code be as small as possible. The MDP is an inherently concurrent processor with efficient mechanisms for sending and receiving messages; the compiler takes advantage of these mechanisms. The MDP's tagged architecture allows very efficient support of object-oriented languages such as Concurrent Smalltalk. The initial goals for the MDP were to have the MDP execute about twenty instructions per method and contain 4096 words of memory. This compiler shows that these goals are too optimistic -- most methods are longer, both in terms of code size and running time. Thus, the memory size of the MDP should be increased.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

Retargeting of pre-set regions on chromosome for high gene expression in mammalian cells

We have developed a system to hunt and reuse special gene integration sites that allow for high and stable gene expression. A vector, named pRGFP8, was constructed. The plasmid pRGFP8 contains a reporter gene, gfp2 and two extraneous DNA fragments. The gene gfp2 makes it possible to screen the high expression regions on the chromosome. The extraneous DNA fragments can help to create the unique loci on the chromosome and increase the gene targeting frequency by increasing the homology. After transfection into Chinese hamster ovary cells (CHO) cells, the linearized pRGFP8 can integrate into the chromosome of the host cells and form the unique sites. With FACS, 90 millions transfected cells were sorted and the cells with strongest GFP expression were isolated, and then 8 stable high expression GFP CHO cell lines were selected as candidates for the new host cell. Taking the unique site created by pRGFP8 on the chromosome in the new host cells as a targeting locus, the gfp2 gene was replaced with the gene of interest, human ifngamma, by transfecting the targeting plasmid pRIH-IFN. Then using FACS, the cells with the dimmest GFP fluorescence were selected. These cells showed they had strong abilities to produce the protein of interest, IFN-gamma. During the gene targeting experiment, we found there is positive correlation between the fluorescence density of the GFP CHO host cells and the specific production rate of IFN-gamma. This result shows that the strategy in our expression system is correct: the production of the interesting protein increases with the increase fluorescence of the GFP host cells. This system, the new host cell lines and the targeting vector, can be utilized for highly expressing the gene of interest. More importantly, by using FACS, we can fully screen all the transfected cells, which can reduce the chances of losing the best cells.