999 resultados para ANALOG PERFORMANCE


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Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

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This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45 degrees rotated SOI substrates comparing their performance with standard MuGFETs fabricated without substrate rotation. Different fin widths are studied for temperatures ranging from 250 K up to 400 K. The results of transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and unit-gain frequency are studied. It is observed that the substrate rotation improves the carrier mobility of narrow MuGFETs at any temperature because of the changing in the conduction plane at the sidewalls from (1 1 0) to (1 0 0). For lower temperatures, the improvement of the carrier mobility of rotated MuGFETs is more noticeable as well as the rate of mobility improvement with the temperature decrease is larger. The output conductance is weakly affected by the substrate rotation. Although this improvement in the transconductance of rotated MuGFETs is negligibly transferred to the intrinsic voltage gain, the unity-gain frequency of rotated device is improved due to the larger carrier mobility in the entire range of temperatures studied. (C) 2011 Elsevier Ltd. All rights reserved.

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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

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In this work, the impact of global and/or local strain engineering techniques on tri-gate p- and nMuGFETs performance is experimentally evaluated. Multiple gate structures were analyzed through basic and analog performance parameters for four different splits processed with different strain-engineering techniques (unstrained, uniaxial, biaxial and uniaxial+biaxial stress). While n-channel devices with narrow fins present a worse analog behavior, biaxial stress promotes the electron mobility for larger devices increasing the voltage gain. Besides the voltage gain, the transconductance, output conductance and Early Voltage are also evaluated. Although pMuGFETs are less affected by the strain engineering, they present better analog behavior for all studied devices.

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In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance. Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristic; and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications. (C) 2011 Elsevier Ltd. All rights reserved.

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In this work the proton irradiation influence on Multiple Gate MOSFETs (MuGFETs) performance is investigated. This analysis was performed through basic and analog parameters considering four different splits (unstrained, uniaxial, biaxial, uniaxial+biaxial). Although the influence of radiation is more pronounced for p-channel devices, in pMuGFETs devices, the radiation promotes a higher immunity to the back interface conduction resulting in the analog performance improvement. On the other hand, the proton irradiation results in a degradation of the post-irradiated n-channel transistors behavior. The unit gain frequency showed to be strongly dependent on stress efficiency and the radiation results in an increase of the unit gain frequency for splits with high stress effectiveness for both cases p- and nMuGFETs.

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Este trabalho teve como objetivo estudar os transistores de tunelamento por efeito de campo em estruturas de nanofio (NW-TFET), sendo realizado através de analises com base em explicações teóricas, simulações numéricas e medidas experimentais. A fim de avaliar melhorar o desempenho do NW-TFET, este trabalho utilizou dispositivos com diferentes materiais de fonte, sendo eles: Si, liga SiGe e Ge, além da variação da espessura de HfO2 no material do dielétrico de porta. Com o auxílio de simulações numéricas foram obtidos os diagramas de bandas de energia dos dispositivos NW-TFET com fonte de Si0,73Ge0,27 e foi analisada a influência de cada um dos mecanismos de transporte de portadores para diversas condições de polarização, sendo observado a predominância da influência da recombinação e geração Shockley-Read-Hall (SRH) na corrente de desligamento, do tunelamento induzido por armadilhas (TAT) para baixos valores de tensões de porta (0,5V > VGS > 1,5V) e do tunelamento direto de banda para banda (BTBT) para maiores valores tensões de porta (VGS > 1,5V). A predominância de cada um desses mecanismos de transporte foi posteriormente comprovada com a utilização do método de Arrhenius, sendo este método adotado em todas as análises do trabalho. O comportamento relativamente constante da corrente dos NW-TFETs com a temperatura na região de BTBT tem chamado a atenção e por isso foi realizado o estudo dos parâmetros analógicos em função da temperatura. Este estudo foi realizado comparando a influência dos diferentes materiais de fonte. O uso de Ge na fonte, permitiu a melhora na corrente de tunelamento, devido à sua menor banda proibida, aumentando a corrente de funcionamento (ION) e a transcondutância do dispositivo. Porém, devido à forte dependência de BTBT com o campo elétrico, o uso de Ge na fonte resulta em uma maior degradação da condutância de saída. Entretanto, a redução da espessura de HfO2 no dielétrico de porta resultou no melhor acoplamento eletrostático, também aumentando a corrente de tunelamento, fazendo com que o dispositivo com fonte Ge e menor HfO2 apresentasse melhores resultados analógicos quando comparado ao puramente de Si. O uso de diferentes materiais durante o processo de fabricação induz ao aumento de defeitos nas interfaces do dispositivo. Ao longo deste trabalho foi realizado o estudo da influência da densidade de armadilhas de interface na corrente do dispositivo, demonstrando uma relação direta com o TAT e a formação de uma região de platô nas curvas de IDS x VGS, além de uma forte dependência com a temperatura, aumentando a degradação da corrente para temperaturas mais altas. Além disso, o uso de Ge introduziu maior número de impurezas no óxido, e através do estudo de ruído foi observado que o aumento na densidade de armadilhas no óxido resultou no aumento do ruído flicker em baixa frequência, que para o TFET, ocorre devido ao armadilhamento e desarmadilhamento de elétrons na região do óxido. E mais uma vez, o melhor acoplamento eletrostático devido a redução da espessura de HfO2, resultou na redução desse ruído tornando-se melhor quando comparado à um TFET puramente de Si. Neste trabalho foi proposto um modelo de ruído em baixa frequência para o NW-TFET baseado no modelo para MOSFET. Foram realizadas apenas algumas modificações, e assim, obtendo uma boa concordância com os resultados experimentais na região onde o BTBT é o mecanismo de condução predominante.

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This paper introduces a new highspeed single-way analog switch which has both highspeed high-resolution mono-direction analog transmission gate function and high-speed digital logic gate function with normal bipolar technology. The analysis of static and transient switching performances as an analog transmission gate is emphasized in the paper. In order to reduce the plug-in effect on high-speed high-resolution systems, an optimum design scheme is also given. This scheme is to achieve accelerated dynamic response with very low bias power dissipation. The analysis of PSPICE simulation as well as the circuit test results confirms the feasibility of the scheme. Now, the circuit has been applied effectively to the designs of novel highspeed A/D and D/A converters.

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In this paper, weconsider switch-and-stay combining (SSC) in two-way relay systems with two amplify-and-forward relays, one of which is activated to assist the information exchange between the two sources. The system operates in either analog network coding (ANC) protocol where the communication is only achieved with the help of the active relay or timedivision broadcast (TDBC) protocol where the direct link between two sources can be utilized to exploit more diversity gain. In both cases, we study the outage probability and bit error rate (BER) for Rayleigh fading channels. In particular, we derive closed-form lower bounds for the outage probability and the average BER, which remain tight for different fading conditions. We also present asymptotic analysis for both the outage probability and the average BER at high signalto-noise ratio. It is shown that SSC can achieve the full diversity order in two-way relay systems for both ANC and TDBC protocols with proper switching thresholds. Copyright © 2014 John Wiley & Sons, Ltd.

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Texas State Department of Highways and Public Transportation, Transportation Planning Division, Austin

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New substation technology, such as non-conventional instrument transformers,and a need to reduce design and construction costs, are driving the adoption of Ethernet based digital process bus networks for high voltage substations. Protection and control applications can share a process bus, making more efficient use of the network infrastructure. This paper classifies and defines performance requirements for the protocols used in a process bus on the basis of application. These include GOOSE, SNMP and IEC 61850-9-2 sampled values. A method, based on the Multiple Spanning Tree Protocol (MSTP) and virtual local area networks, is presented that separates management and monitoring traffic from the rest of the process bus. A quantitative investigation of the interaction between various protocols used in a process bus is described. These tests also validate the effectiveness of the MSTP based traffic segregation method. While this paper focusses on a substation automation network, the results are applicable to other real-time industrial networks that implement multiple protocols. High volume sampled value data and time-critical circuit breaker tripping commands do not interact on a full duplex switched Ethernet network, even under very high network load conditions. This enables an efficient digital network to replace a large number of conventional analog connections between control rooms and high voltage switchyards.

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In this paper, a novel 2×2 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) testbed based on an Analog Devices AD9361 highly integrated radio frequency (RF) agile transceiver was specifically implemented for the purpose of estimating and analyzing MIMO-OFDM channel capacity in vehicle-to-infrastructure (V2I) environments using the 920 MHz industrial, scientific, and medical (ISM) band. We implemented two-dimensional discrete cosine transform-based filtering to reduce the channel estimation errors and show its effectiveness on our measurement results. We have also analyzed the effects of channel estimation error on the MIMO channel capacity by simulation. Three different scenarios of subcarrier spacing were investigated which correspond to IEEE 802.11p, Long-Term Evolution (LTE), and Digital Video Broadcasting Terrestrial (DVB-T)(2k) standards. An extensive MIMO-OFDM V2I channel measurement campaign was performed in a suburban environment. Analysis of the measured MIMO channel capacity results as a function of the transmitter-to-receiver (TX-RX) separation distance up to 250 m shows that the variance of the MIMO channel capacity is larger for the near-range line-of-sight (LOS) scenarios than for the long-range non-LOS cases, using a fixed receiver signal-to-noise ratio (SNR) criterion. We observed that the largest capacity values were achieved at LOS propagation despite the common assumption of a degenerated MIMO channel in LOS. We consider that this is due to the large angular spacing between MIMO subchannels which occurs when the receiver vehicle rooftop antennas pass by the fixed transmitter antennas at close range, causing MIMO subchannels to be orthogonal. In addition, analysis on the effects of different subcarrier spacings on MIMO-OFDM channel capacity showed negligible differences in mean channel capacity for the subcarrier spacing range investigated. Measured channels described in this paper are available on request.

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A new performance metric, Peak-Error Ratio (PER) has been presented to benchmark the performance of a class of neuron circuits to realize neuron activation function (NAF) and its derivative (DNAF). Neuron circuits, biased in subthreshold region, based on the asymmetric cross-coupled differential pair configuration and conventional configuration of applying small external offset voltage at the input have been compared on the basis of PER. It is shown that the technique of using transistor asymmetry in a cross-coupled differential pair performs on-par with that of applying external offset voltage. The neuron circuits have been experimentally prototyped and characterized as a proof of concept on the 1.5 mu m AMI technology.