Modeling multiple state electrostatically formed nanowire transistors

The present thesis work proposes a new physical equivalent circuit model for a recently proposed semiconductor transistor, a 2-drain MSET (Multiple State Electrostatically Formed Nanowire Transistor). It presents a new software-based experimental setup that has been developed for carrying out numerical simulations on the device and on equivalent circuits. As of 2015, we have already approached the scaling limits of the ubiquitous CMOS technology that has been in the forefront of mainstream technological advancement, so many researchers are exploring different ideas in the realm of electrical devices for logical applications, among them MSET transistors. The idea that underlies MSETs is that a single multiple-terminal device could replace many traditional transistors. In particular a 2-drain MSET is akin to a silicon multiplexer, consisting in a Junction FET with independent gates, but with a split drain, so that a voltage-controlled conductive path can connect either of the drains to the source. The first chapter of this work presents the theory of classical JFETs and its common equivalent circuit models. The physical model and its derivation are presented, the current state of equivalent circuits for the JFET is discussed. A physical model of a JFET with two independent gates has been developed, deriving it from previous results, and is presented at the end of the chapter. A review of the characteristics of MSET device is shown in chapter 2. In this chapter, the proposed physical model and its formulation are presented. A listing for the SPICE model was attached as an appendix at the end of this document. Chapter 3 concerns the results of the numerical simulations on the device. At first the research for a suitable geometry is discussed and then comparisons between results from finite-elements simulations and equivalent circuit runs are made. Where points of challenging divergence were found between the two numerical results, the relevant physical processes are discussed. In the fourth chapter the experimental setup is discussed. The GUI-based environments that allow to explore the four-dimensional solution space and to analyze the physical variables inside the device are described. It is shown how this software project has been structured to overcome technical challenges in structuring multiple simulations in sequence, and to provide for a flexible platform for future research in the field.

Switching performance of epitaxially grown normally-off 4H-SiC JFET

Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6-10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5-1.8kV was realized at VGS = -5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design. © (2009) Trans Tech Publications, Switzerland.

Optimising the dynamic performance of an all-wide-bandgap cascode switch

A SPICE simulation model of a novel cascode switch that combines a high voltage normally-on silicon carbide (SiC) junction field effect transistor (JFET) with a low voltage enhancement-mode gallium nitride field effect transistor (eGaN FET) has been developed, with the aim of optimising cascode switching performance. The effect of gate resistance on stability and switching losses is investigated and optimum values chosen. The effects of stray inductance on cascode switching performance are considered and the benefits of low inductance packaging discussed. The use of a positive JFET gate bias in a cascode switch is shown to reduce switching losses as well as reducing on-state losses. The findings of the simulation are used to produce a list of priorities for the design and layout of wide-bandgap cascode switches, relevant to both SiC and GaN high voltage devices. © 2013 IEEE.

A study of the effects metal residues in poly(9,9-dioctylfluorene) have on field-effect transistor device characteristics

The amount of metal residues from organometallic reagents used in preparation of poly(9,9-dioctylfluorene) by palladium catalysed Suzuki and nickel-induced Yamamoto polycondensations have been determined, and their effect upon the behaviour of the polymer in field-effect transistors (FETs) has been measured. The metal levels from material polymerised by Suzuki method were found to be much higher than from that made by the Yamamoto procedure. Simple treatment of the polymers with suitable metal trapping reagents lowered the metal levels significantly, with EDTA giving best results for nickel and triphenylphosphine for palladium. Comparison of the behaviour of FETs using polyfluorenes with varying levels of metal contamination, showed that the metal residues have little effect upon the mobility values, but often affect the degree of hysteresis, possibly acting as charge traps. Satisfactory device performances were obtained from polymer with palladium levels of 2000 μg/g suggesting that complete removal of metal residues may not be necessary for satisfactory device performance.

Synthesis, characterization and organic field effect transistor performance of a diketopyrrolopyrrole-fluorenone copolymer

A diketopyrrolopyrrole (DPP) with fluorenone (FN) based low band gap alternating copolymer (PDPPT-alt-FN) has been synthesized via Suzuki coupling. PDPPT-alt-FN exhibits a deep HOMO level with a lower band gap. Fabricated organic thin film transistors using PDPPT-alt-FN as a channel semiconductor show p-channel behaviour with the highest hole mobility of 0.083 cm2 V-1 s-1 measured in air.

High mobility organic thin film transistor and efficient photovoltaic devices using versatile donor-acceptor polymer semiconductor by molecular design

In this work, we report a novel donor-acceptor based solution processable low band gap polymer semiconductor, PDPP-TNT, synthesized via Suzuki coupling using condensed diketopyrrolopyrrole (DPP) as an acceptor moiety with a fused naphthalene donor building block in the polymer backbone. This polymer exhibits p-channel charge transport characteristics when used as the active semiconductor in organic thin-film transistor (OTFT) devices. The hole mobilities of 0.65 cm2 V-1 s-1 and 0.98 cm2 V -1 s-1 are achieved respectively in bottom gate and dual gate OTFT devices with on/off ratios in the range of 105 to 10 7. Additionally, due to its appropriate HOMO (5.29 eV) energy level and optimum optical band gap (1.50 eV), PDPP-TNT is a promising candidate for organic photovoltaic (OPV) applications. When this polymer semiconductor is used as a donor and PC71BM as an acceptor in OPV devices, high power conversion efficiencies (PCE) of 4.7% are obtained. Such high mobility values in OTFTs and high PCE in OPV make PDPP-TNT a very promising polymer semiconductor for a wide range of applications in organic electronics.

Furan containing diketopyrrolopyrrole copolymers : synthesis, characterization, organic field effect transistor performance and photovoltaic properties

In this work, we report design, synthesis and characterization of solution processable low band gap polymer semiconductors, poly{3,6-difuran-2-yl-2,5-di(2- octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-phenylene} (PDPP-FPF), poly{3,6-difuran-2-yl-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1, 4-dione-alt-naphthalene} (PDPP-FNF) and poly{3,6-difuran-2-yl-2,5-di(2- octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-anthracene} (PDPP-FAF) using the furan-containing 3,6-di(furan-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione (DBF) building block. As DBF acts as an acceptor moiety, a series of donor-acceptor (D-A) copolymers can be generated when it is attached alternatively with phenylene, naphthalene or anthracene donor comonomer blocks. Optical and electrochemical characterization of thin films of these polymers reveals band gaps in the range of 1.55-1.64 eV. These polymers exhibit excellent hole mobility when used as the active layer in organic thin-film transistor (OTFT) devices. Among the series, the highest hole mobility of 0.11 cm 2 V -1 s -1 is achieved in bottom gate and top-contact OTFT devices using PDPP-FNF. When these polymers are used as a donor and [70]PCBM as the acceptor in organic photovoltaic (OPV) devices, power conversion efficiencies (PCE) of 2.5 and 2.6% are obtained for PDPP-FAF and PDPP-FNF polymers, respectively. Such mobility values in OTFTs and performance in OPV make furan-containing DBF a very promising block for designing new polymer semiconductors for a wide range of organic electronic applications.

Density of trap states in a polymer field-effect transistor

We report a more accurate method to determine the density of trap states in a polymer field-effect transistor. In the approach, we describe in this letter, we take into consideration the sub-threshold behavior in the calculation of the density of trap states. This is very important since the sub-threshold regime of operation extends to fairly large gate voltages in these disordered semiconductor based transistors. We employ the sub-threshold drift-limited mobility model (for sub-threshold response) and the conventional linear mobility model for above threshold response. The combined use of these two models allows us to extract the density of states from charge transport data much more accurately. We demonstrate our approach by analyzing data from diketopyrrolopyrrole based co-polymer transistors with high mobility. This approach will also work well for other disordered semiconductors in which sub-threshold conduction is important.

Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor

A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poisson's equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channel center to the surface. We demonstrated, using the proposed model, that the channel potential versus gate voltage characteristics for the devices having equal channel lengths but different thicknesses pass through a single common point (termed ``crossover point''). Based on the potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects (SCE), the effective subthreshold slope factor is mainly dictated by the potential close to the channel center rather than the surface. SCEs and drain-induced barrier lowering are also assessed using the proposed model and validated against a professional numerical device simulator.

Protection and Switching-Aid Networks for Transistor Bridge Inverters

The present trend in the industry is towards the use of power transistors in the development of efficient Pulsewidth Modulated (PWM) inverters, because of their operation at high frequency, simplicity of turn-off, and low commutation losses compared to the technology using thyristors. But the protection of power transistors, minimization of switching power loss, and design of base drive circuit are very important for a reliable operation of the system. The requirements, analysis, and a simplified procedure for calculation of the switching-aid network components are presented. The transistor is protected against short circuit using a modified autoregulated and autoprotection drive circuit. The experimental results show that the switching power loss and voltage stress in the device can be reduced by suitable choice of the switching-aid network component values.

Fabrication and characterization of polyterpenol as an insulating layer and incorporated organic field effect transistor

A non-synthetic polymer material, polyterpenol, was fabricated using a dry polymerization process namely RF plasma polymerization from an environmentally friendly monomer and its surface, optical and electrical properties investigated. Polyterpenol films were found to be transparent over the visible wavelength range, with a smooth surface with an average roughness of less than 0.4 nm and hardness of 0.4 GPa. The dielectric constant of 3.4 for polyterpenol was higher than that of the conventional polymer materials used in the organic electronic devices. The non-synthetic polymer material was then implemented as a surface modification of the gate insulator in field effect transistor (OFET) and the properties of the device were examined. In comparison to the similar device without the polymer insulating layer, the polyterpenol based OFET device showed significant improvements. The addition of the polyterpenol interlayer in the OFET shifted the threshold voltage significantly; + 20 V to -3 V. The presence of trapped charge was not observed in the polyterpenol interlayer. This assisted in the improvement of effective mobility from 0.012 to 0.021 cm 2/Vs. The switching property of the polyterpenol based OFET was also improved; 107 compared to 104. The results showed that the non-synthetic polyterpenol polymer film is a promising candidate of insulators in electronic devices.

The formation of a p-n junction in a polymer electrolyte top-gated bilayer graphene transistor

We show simultaneous p- and n-type carrier injection in a bilayer graphene channel by varying the longitudinal bias across the channel and the top-gate voltage. The top gate is applied electrochemically using solid polymer electrolyte and the gate capacitance is measured to be 1.5 microF cm(-2), a value about 125 times higher than the conventional SiO(2) back-gate capacitance. Unlike the single-layer graphene, the drain-source current does not saturate on varying the drain-source bias voltage. The energy gap opened between the valence and conduction bands using top- and back-gate geometry is estimated.

Photoimpedance characterization of polymer field-effect transistor

The small signal ac response is measured across the source-drain terminals of poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene) field-effect transistor under dc bias to obtain the equivalent circuit parameters in the dark, and under a monochromatic light (540 nm) of various intensities. The numerically simulated response based on these parameters shows deviation at low frequency which is related to the charge accumulation at the interface and the contact resistance at the electrodes. This method can be used to differentiate the photophysical phenomena occurring in the bulk from that at the metal-semiconductor interface for polymer field-effect transistors. ©2009 American Institute of Physics

Ultralow noise field-effect transistor from multilayer graphene

We present low-frequency electrical resistance fluctuations, or noise, in graphene-based field-effect devices with varying number of layers. In single-layer devices, the noise magnitude decreases with increasing carrier density, which behaved oppositely in the devices with two or larger number of layers accompanied by a suppression in noise magnitude by more than two orders in the latter case. This behavior can be explained from the influence of external electric field on graphene band structure, and provides a simple transport-based route to isolate single-layer graphene devices from those with multiple layers. ©2009 American Institute of Physics

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor

In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long channel cylindrical body structure. The potential distribution at each and every point of the of the wire is derived with a closed form solution of two dimensional Poisson's equation, which is then used to model the threshold voltage. Proposed model can be treated as a generalized model, which is valid for both surround gate and semi-surround gate cylindrical transistors. The accuracy of proposed model is verified for different device geometry against the results obtained from three dimensional numerical device simulators and close agreement is observed.