MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Analysis-aware design of embedded systems software

In the past many different methodologies have been devised to support software development and different sets of methodologies have been developed to support the analysis of software artefacts. We have identified this mismatch as one of the causes of the poor reliability of embedded systems software. The issue with software development styles is that they are ``analysis-agnostic.'' They do not try to structure the code in a way that lends itself to analysis. The analysis is usually applied post-mortem after the software was developed and it requires a large amount of effort. The issue with software analysis methodologies is that they do not exploit available information about the system being analyzed.

In this thesis we address the above issues by developing a new methodology, called "analysis-aware" design, that links software development styles with the capabilities of analysis tools. This methodology forms the basis of a framework for interactive software development. The framework consists of an executable specification language and a set of analysis tools based on static analysis, testing, and model checking. The language enforces an analysis-friendly code structure and offers primitives that allow users to implement their own testers and model checkers directly in the language. We introduce a new approach to static analysis that takes advantage of the capabilities of a rule-based engine. We have applied the analysis-aware methodology to the development of a smart home application.

Cryptographic coprocessors for embedded systems

In the field of embedded systems design, coprocessors play an important role as a component to increase performance. Many embedded systems are built around a small General Purpose Processor (GPP). If the GPP cannot meet the performance requirements for a certain operation, a coprocessor can be included in the design. The GPP can then offload the computationally intensive operation to the coprocessor; thus increasing the performance of the overall system. A common application of coprocessors is the acceleration of cryptographic algorithms. The work presented in this thesis discusses coprocessor architectures for various cryptographic algorithms that are found in many cryptographic protocols. Their performance is then analysed on a Field Programmable Gate Array (FPGA) platform. Firstly, the acceleration of Elliptic Curve Cryptography (ECC) algorithms is investigated through the use of instruction set extension of a GPP. The performance of these algorithms in a full hardware implementation is then investigated, and an architecture for the acceleration the ECC based digital signature algorithm is developed. Hash functions are also an important component of a cryptographic system. The FPGA implementation of recent hash function designs from the SHA-3 competition are discussed and a fair comparison methodology for hash functions presented. Many cryptographic protocols involve the generation of random data, for keys or nonces. This requires a True Random Number Generator (TRNG) to be present in the system. Various TRNG designs are discussed and a secure implementation, including post-processing and failure detection, is introduced. Finally, a coprocessor for the acceleration of operations at the protocol level will be discussed, where, a novel aspect of the design is the secure method in which private-key data is handled

Towards policy-based self-configuration of embedded systems

This paper describes work towards the deployment of flexible self-management into real-time embedded systems. A challenging project which focuses specifically on the development of a dynamic, adaptive automotive middleware is described, and the specific self-management requirements of this project are discussed. These requirements have been identified through the refinement of a wide-ranging set of use cases requiring context-sensitive behaviours. A sample of these use-cases is presented to illustrate the extent of the demands for self-management. The strategy that has been adopted to achieve self-management, based on the use of policies is presented. The embedded and real-time nature of the target system brings the constraints that dynamic adaptation capabilities must not require changes to the run-time code (except during hot update of complete binary modules), adaptation decisions must have low latency, and because the target platforms are resource-constrained the self-management mechanism have low resource requirements (especially in terms of processing and memory). Policy-based computing is thus and ideal candidate for achieving the self-management because the policy itself is loaded at run-time and can be replaced or changed in the future in the same way that a data file is loaded. Policies represent a relatively low complexity and low risk means of achieving self-management, with low run-time costs. Policies can be stored internally in ROM (such as default policies) as well as externally to the system. The architecture of a designed-for-purpose powerful yet lightweight policy library is described. A suitable evaluation platform, supporting the whole life-cycle of feasibility analysis, concept evaluation, development, rigorous testing and behavioural validation has been devised and is described.

An optimized stereo vision implementation for embedded systems: application to RGB and Infra-Red images

The aim of this paper is to demonstrate the applicability and the effectiveness of a computationally demanding stereo matching algorithm in different lowcost and low-complexity embedded devices, by focusing on the analysis of timing and image quality performances. Various optimizations have been implemented to allow its deployment on specific hardware architectures while decreasing memory and processing time requirements: (1) reduction of color channel information and resolution for input images, (2) low-level software optimizations such as parallel computation, replacement of function calls or loop unrolling, (3) reduction of redundant data structures and internal data representation. The feasibility of a stereovision system on a low cost platform is evaluated by using standard datasets and images taken from Infra-Red (IR) cameras. Analysis of the resulting disparity map accuracy with respect to a full-size dataset is performed as well as the testing of suboptimal solutions

A framework for the development of parallel and distributed real-time embedded systems

Embedded real-time applications increasingly present high computation requirements, which need to be completed within specific deadlines, but that present highly variable patterns, depending on the set of data available in a determined instant. The current trend to provide parallel processing in the embedded domain allows providing higher processing power; however, it does not address the variability in the processing pattern. Dimensioning each device for its worst-case scenario implies lower average utilization, and increased available, but unusable, processing in the overall system. A solution for this problem is to extend the parallel execution of the applications, allowing networked nodes to distribute the workload, on peak situations, to neighbour nodes. In this context, this report proposes a framework to develop parallel and distributed real-time embedded applications, transparently using OpenMP and Message Passing Interface (MPI), within a programming model based on OpenMP. The technical report also devises an integrated timing model, which enables the structured reasoning on the timing behaviour of these hybrid architectures.

Efficient schedulability tests for real-time embedded systems with urgent routines

Task scheduling is one of the key mechanisms to ensure timeliness in embedded real-time systems. Such systems have often the need to execute not only application tasks but also some urgent routines (e.g. error-detection actions, consistency checkers, interrupt handlers) with minimum latency. Although fixed-priority schedulers such as Rate-Monotonic (RM) are in line with this need, they usually make a low processor utilization available to the system. Moreover, this availability usually decreases with the number of considered tasks. If dynamic-priority schedulers such as Earliest Deadline First (EDF) are applied instead, high system utilization can be guaranteed but the minimum latency for executing urgent routines may not be ensured. In this paper we describe a scheduling model according to which urgent routines are executed at the highest priority level and all other system tasks are scheduled by EDF. We show that the guaranteed processor utilization for the assumed scheduling model is at least as high as the one provided by RM for two tasks, namely 2(2√−1). Seven polynomial time tests for checking the system timeliness are derived and proved correct. The proposed tests are compared against each other and to an exact but exponential running time test.

SCIL processor : a common intermediate language processor for embedded systems

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Entwurf und Betrieb von Regelungs- und Monitoringsystemen für dezentrale Energiesysteme auf der Basis von verteilten Embedded Systems

Nach einem einleitenden ersten Kapitel wird im zweiten Kapitel der Stand der Technik für Regelungs- und Monitoringsysteme mit vernetzten Systemen dargestellt. Daraus wird die Motivation zur Entwicklung neuer, kostengünstiger Systeme abgeleitet. Im dritten Kapitel folgt eine Darstellung der verschiedenen Arten marktverfügbarer Embedded Systems und dafür geeigneter Betriebs­systeme. Anforderungen an verteilte Regelungssysteme, unterschiedliche Strukturen dieser Systeme und deren Vor- und Nachteile sind Gegenstand des vierten Kapitels. Anhand von Beispielen aus den Bereichen Erzeugungsmanagement für den Betrieb von KWK-Anlagen, Energieverbrauchsmonitoring und Smart-Metering wird der Einsatz von verteilten Regelungs- und Monitoringsystemen im fünften Kapitel dargestellt. Im folgenden sechsten Kapitel wird die Bedeutung normierter Kommunikation für den Einsatz in verteilten Systemen sowie dafür vorhandene Standards aus der elektrischen Energieversorgungstechnik und der Automatisierungstechnik behandelt. Der Stand der Internet-Technik für verteilte Systeme ist Gegenstand des siebten Kapitels. Dabei werden zunächst die verschiedenen drahtlosen und drahtgebundenen Kommunikationsmedien vorgestellt und ihre Eigenschaften und die Rand­bedingungen für ihren Einsatz erörtert. Ebenso werden technische Probleme beim Einsatz der Internet-Technik aufgezeigt und Lösungsmöglichkeiten für diese Probleme dargestellt. Es folgt eine Übersicht von Netzwerkdiensten, die für den Betrieb von verteilten Systemen notwendig sind. Außerdem werden Techniken zur Überwachung von verteilten Systemen behandelt. Kapitel acht zeigt Sicherheitsrisiken bei der Nutzung des Internets auf und bewertet verschiedene Techniken zur Absicherung des Netzwerkverkehrs. Kapitel neun stellt ein Internet-basiertes Client-Server-System zur Online-Visualisierung von Anlagendaten im Webbrowser mit Hilfe von Java-Applets und XML-RPC vor. Die Visualisierung von Anlagendaten auf Mobiltelefonen mit Hilfe des Wireless Application Protocol sowie die dafür notwendige Software und Infrastruktur ist Gegenstand des zehnten Kapitels. Im elften Kapitel wird eine neuartige Software für die Simulation von dezentralen Energiesystemen und deren Regelungs­systemen auf Basis von virtuellen Maschinen, virtuellen Netzwerken und einer thermischen Simulationsumgebung vorgestellt sowie deren Anwendung für die Reglerentwicklung erklärt. Verschiedene Techniken für die Installation von Betriebssystemen und Software für die Embedded Systems eines verteilten Systems werden im Kapitel zwölf untersucht. Im Kapitel 13 werden verschiedene Technologien zur Konfiguration und Parametrierung von Regelungssystemen in der industriellen Prozess- und Fertigungs­automatisierung hinsichtlich ihrer Eignung für dezentrale Energiesysteme analysiert. Anschließend wird eine Software zur Installation und Parametrierung von Monitoringsystemen sowie der dazugehörigen Infrastruktur vorgestellt. Kapitel 14 beschäftigt sich mit Anforderungen an die Hardware für verteilte Systeme und mit Maßnahmen zur Erhöhung der Betriebs- und der Datensicherheit. Im 15. Kapitel werden die in den bisherigen Kapiteln vorgestellten Techniken anhand eines großen verteilten Monitoringsystems und anhand eines Power Flow and Power Quality Management Systems auf Basis von verteilten Embedded Systems evaluiert. Kapitel 16 fasst die Ergebnisse der Arbeit zusammen und enthält einen Ausblick auf zukünftige Entwicklungen.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

Model driven design for embedded systems

Questo lavoro di tesi si focalizza sulla modellazione di sistemi software in grado far interagire piattaforme elettroniche differenti tra loro.