616 resultados para drain


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This article describes how to use a siphon to drain floodwaters. A siphon is a tube that conveys water to a lower level via point above the upper water level by gravity. A siphon can be set up to drain existing floodwaters more quickly than they would naturally and can also prevent flooding. Siphons are particularly useful in situations where no pump is available, and a drainage point exists lower than the level of the floodwaters. Some case studies are presented.

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Within the cardiac high dependency unit it is currently a member of the surgical team who makes the decision for a patient's chest drain to be removed after cardiac surgery. This has often resulted in delays in discharging one patient and therefore in admitting the next. A pilot study was carried out using a working standard that had been developed, incorporating an algorithmic model. The results have enabled nursing staff in a cardiac high dependency unit to undertake this responsibility independently.

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In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

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The performance characteristics of a junction field-effect transistor (j.f.e.t.) are evaluated considering the presence of the gap between the gate electrode and the source and drain terminals. It is concluded that the effect of the gap is to demand a higher drain voltage to maintain the same drain current. So long as the device is operated at the same drain current, the presence of the gap does not change the performance of the device as an amplifier. The nature of the performance of the device as a variable resistor is not affected by the gap if it is less than or equal to the physical height of the channel. For gap lengths larger than the channel height, the effect of the gap is to add a series resistance in the drain.

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The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

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Most of the cities in India are undergoing rapid development in recent decades, and many rural localities are undergoing transformation to urban hotspots. These developments have associated land use/land cover (LULC) change that effects runoff response from catchments, which is often evident in the form of increase in runoff peaks, volume and velocity in drain network. Often most of the existing storm water drains are in dilapidated stage owing to improper maintenance or inadequate design. The drains are conventionally designed using procedures that are based on some anticipated future conditions. Further, values of parameters/variables associated with design of the network are traditionally considered to be deterministic. However, in reality, the parameters/variables have uncertainty due to natural and/or inherent randomness. There is a need to consider the uncertainties for designing a storm water drain network that can effectively convey the discharge. The present study evaluates performance of an existing storm water drain network in Bangalore, India, through reliability analysis by Advance First Order Second Moment (AFOSM) method. In the reliability analysis, parameters that are considered to be random variables are roughness coefficient, slope and conduit dimensions. Performance of the existing network is evaluated considering three failure modes. The first failure mode occurs when runoff exceeds capacity of the storm water drain network, while the second failure mode occurs when the actual flow velocity in the storm water drain network exceeds the maximum allowable velocity for erosion control, whereas the third failure mode occurs when the minimum flow velocity is less than the minimum allowable velocity for deposition control. In the analysis, runoff generated from subcatchments of the study area and flow velocity in storm water drains are estimated using Storm Water Management Model (SWMM). Results from the study are presented and discussed. The reliability values are low under the three failure modes, indicating a need to redesign several of the conduits to improve their reliability. This study finds use in devising plans for expansion of the Bangalore storm water drain system. (C) 2015 The Authors. Published by Elsevier B.V.

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In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

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Many fisheries are potentially very valuable. According to a recent report by the World Bank and the FAO (2008), global fisheries rents could be as high as US$ 40-60 billion annually on a sustainable basis. However, according to the report, due to the “common property problem”, most fisheries of the world are severely overexploited and generate no economic rents. The Lake Victoria Nile perch fishery could be among the most valuable fisheries in the world. Unfortunately, also this fishery has fallen prey to the common property problem with excessive fishing effort, dwindling stocks and declining profitability. As a result, there is a large and growing rents loss in this fishery (compared to the optimal) reducing economic welfare and economic growth opportunities in the countries sharing this fishery. As in other fisheries, the biological and economic recovery of this fishery can only come though improved fisheries management

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Two-dimensional MOS device simulation programs such as MINIMOS left bracket 1 right bracket are limited in their validity due to assumptions made in defining the initial two-dimensional source/drain profiles. The two options available to define source/drain regions both construct a two-dimensional profile from one-dimensional profiles normal to the surface. Inaccuracies in forming these source/drain profiles can be expected to effect predicted device characteristics as channel dimensions of the device are reduced. This paper examines these changes by interfacing numerically similated two dimensional source/drain profiles to MINIMOS and comparing predicted I//D-V//D characteristics with 2-D interfacing, 2-D profiles constructed from interfaced 1-D profiles and MINIMOS self generated profiles. Data obtained for simulations of 3 mu m N and P channel devices are presented.