A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Hardware reduction in digital delta-sigma modulators via error masking - part I: MASH DDSM

Two classes of techniques have been developed to whiten the quantization noise in digital delta-sigma modulators (DDSMs): deterministic and stochastic. In this two-part paper, a design methodology for reduced-complexity DDSMs is presented. The design methodology is based on error masking. Rules for selecting the word lengths of the stages in multistage architectures are presented. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation and experimental results confirm theoretical predictions. Part I addresses MultistAge noise SHaping (MASH) DDSMs; Part II focuses on single-quantizer DDSMs..

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A Novel 0.72-6.2GHz Continuously-Tunable Delta Sigma Fractional-N Frequency Synthesizer

This paper presents a wideband Delta Sigma-based fractional-N synthesizer with three integrated quadrature VCOs for multiple-input multiple-output (MIMO) wireless communication applications. It continuously covers a wide range frequency from 0.72GHz to 6.2GHz that is suitable for multiple communication standards. The synthesizer is designed in 0.13-um RE CMOS process. The dual clock full differential multi-modulus divide (MMD) with low power consumption can operate over 9GHz under the worst condition. In the whole range frequency from 0.72GHz to 6.2GHz, the maximal tuning range of the QVCOs reaches 33.09% and their phase noise is -119d8/Hz similar to 124d8/Hz @1MHz. Its current is less than 12mA at a 1.2V voltage supply when it operates at the highest frequency of 6.2GHz.

The effect of clock jitter on the performance of continuous-time delta-sigma ADC for GNSS signals

Next generation Global Navigation Satellite System (GNSS) receivers will operate in multiple navigation bands. An efficient way to achieve this with lower power and cost is to employ BandPass Sampling (BPS); nevertheless, the sampling operation injects large amounts of jitter noise, which degrades the performance of the receiver. Continuous–Time (CT) Delta–Sigma (ΔΣ) modulators are capable of suppressing this noise but the impact of clock jitter at the output of the Digital– to–Analog Converter (DAC) in the feedback path of the modulator should be taken into account. This paper presents an analytical approach for describing clock jitter in GNSS receivers when a CT–ΔΣ modulator is utilized for Analog–to–Digital Conversion (ADC). The validity of the presented approach is verified through time–domain simulations using a behavioural model of the fourth–order CT–ΔΣ modulator with 1–bit NRZ DAC feedback pulse.

Delta Sigma Delta-Desmos

Mode of access: Internet.

Development of a sensorimotor algorithm able to deal with unforeseen pushes and its implementation based on VHDL

Development of a Sensorimotor Algorithm Able to Deal with Unforeseen Pushes and Its Implementation Based on VHDL is the title of my thesis which concludes my Bachelor Degree in the Escuela Técnica Superior de Ingeniería y Sistemas de Telecomunicación of the Universidad Politécnica de Madrid. It encloses the overall work I did in the Neurorobotics Research Laboratory from the Beuth Hochschule für Technik Berlin during my ERASMUS year in 2015. This thesis is focused on the field of robotics, specifically an electronic circuit called Cognitive Sensorimotor Loop (CSL) and its control algorithm based on VHDL hardware description language. The reason that makes the CSL special resides in its ability to operate a motor both as a sensor and an actuator. This way, it is possible to achieve a balanced position in any of the robot joints (e.g. the robot manages to stand) without needing any conventional sensor. In other words, the back electromotive force (EMF) induced by the motor coils is measured and the control algorithm responds depending on its magnitude. The CSL circuit contains mainly an analog-to-digital converter (ADC) and a driver. The ADC consists on a delta-sigma modulation which generates a series of bits with a certain percentage of 1's and 0's, proportional to the back EMF. The control algorithm, running in a FPGA, processes the bit frame and outputs a signal for the driver. This driver, which has an H bridge topology, gives the motor the ability to rotate in both directions while it's supplied with the power needed. The objective of this thesis is to document the experiments and overall work done on push ignoring contractive sensorimotor algorithms, meaning sensorimotor algorithms that ignore large magnitude forces (compared to gravity) applied in a short time interval on a pendulum system. This main objective is divided in two sub-objectives: (1) developing a system based on parameterized thresholds and (2) developing a system based on a push bypassing filter. System (1) contains a module that outputs a signal which blocks the main Sensorimotor algorithm when a push is detected. This module has several different parameters as inputs e.g. the back EMF increment to consider a force as a push or the time interval between samples. System (2) consists on a low-pass Infinite Impulse Response digital filter. It cuts any frequency considered faster than a certain push oscillation. This filter required an intensive study on how to implement some functions and data types (fixed or floating point data) not supported by standard VHDL packages. Once this was achieved, the next challenge was to simplify the solution as much as possible, without using non-official user made packages. Both systems behaved with a series of interesting advantages and disadvantages for the elaboration of the document. Stability, reaction time, simplicity or computational load are one of the many factors to be studied in the designed systems. RESUMEN. Development of a Sensorimotor Algorithm Able to Deal with Unforeseen Pushes and Its Implementation Based on VHDL es un Proyecto de Fin de Grado (PFG) que concluye mis estudios en la Escuela Técnica Superior de Ingeniería y Sistemas de Telecomunicación de la Universidad Politécnica de Madrid. En él se documenta el trabajo de investigación que realicé en el Neurorobotics Research Laboratory de la Beuth Hochschule für Technik Berlin durante el año 2015 mediante el programa de intercambio ERASMUS. Este PFG se centra en el campo de la robótica y en concreto en un circuito electrónico llamado Cognitive Sensorimotor Loop (CSL) y su algoritmo de control basado en lenguaje de modelado hardware VHDL. La particularidad del CSL reside en que se consigue que un motor haga las veces tanto de sensor como de actuador. De esta manera es posible que las articulaciones de un robot alcancen una posición de equilibrio (p.ej. el robot se coloca erguido) sin la necesidad de sensores en el sentido estricto de la palabra. Es decir, se mide la propia fuerza electromotriz (FEM) inducida sobre el motor y el algoritmo responde de acuerdo a su magnitud. El circuito CSL se compone de un convertidor analógico-digital (ADC) y un driver. El ADC consiste en un modulador sigma-delta, que genera una serie de bits con un porcentaje de 1's y 0's determinado, en proporción a la magnitud de la FEM inducida. El algoritmo de control, que se ejecuta en una FPGA, procesa esta cadena de bits y genera una señal para el driver. El driver, que posee una topología en puente H, provee al motor de la potencia necesaria y le otorga la capacidad de rotar en cualquiera de las dos direcciones. El objetivo de este PFG es documentar los experimentos y en general el trabajo realizado en algoritmos Sensorimotor que puedan ignorar fuerzas de gran magnitud (en comparación con la gravedad) y aplicadas en una corta ventana de tiempo. En otras palabras, ignorar empujones conservando el comportamiento original frente a la gravedad. Para ello se han desarrollado dos sistemas: uno basado en umbrales parametrizados (1) y otro basado en un filtro de corte ajustable (2). El sistema (1) contiene un módulo que, en el caso de detectar un empujón, genera una señal que bloquea el algoritmo Sensorimotor. Este módulo recibe diferentes parámetros como el incremento necesario de la FEM para que se considere un empujón o la ventana de tiempo para que se considere la existencia de un empujón. El sistema (2) consiste en un filtro digital paso-bajo de respuesta infinita que corta cualquier variación que considere un empujón. Para crear este filtro se requirió un estudio sobre como implementar ciertas funciones y tipos de datos (coma fija o flotante) no soportados por las librerías básicas de VHDL. Tras esto, el objetivo fue simplificar al máximo la solución del problema, sin utilizar paquetes de librerías añadidos. En ambos sistemas aparecen una serie de ventajas e inconvenientes de interés para el documento. La estabilidad, el tiempo de reacción, la simplicidad o la carga computacional son algunas de las muchos factores a estudiar en los sistemas diseñados. Para concluir, también han sido documentadas algunas incorporaciones a los sistemas: una interfaz visual en VGA, un módulo que compensa el offset del ADC o la implementación de una batería de faders MIDI entre otras.

Preparation and electrical properties of new oxide ion conductors Ce6-xDyxMoO15-delta (0.0 <= x <= 1.8)

Ce6-xDyxMoO15-delta (0.0 <= x <= 1.8) were synthesized by modified sol-gel method. Structural and electrical properties were investigated by means of X-ray diffraction (XRD), Raman, X-ray photoelectron spectroscopy (XPS) and electrochemical impedance spectroscopy (EIS). The XRD patterns showed that the materials were single phase with a cubic fluorite structure. Impedance spectroscopy measurement in the temperature range between 350 degrees C and 800 degrees C indicated a sharp increase in conductivity for the system containing small amount of Dy2O3. The Ce5.6Dy0.4MoO15-delta detected to be the best conducting phase with the highest conductivity (sigma(t) = 8.93 x 10(-3) S cm(-1)) is higher than that of Ce5.6Sm0.4MoO15-delta (sigma(t) = 2.93 x 10(-3) S cm(-1)) at 800 degrees C, and the corresponding activation energy of Ce5.6Dy0.4MoO15-delta (0.994 eV) is lower than that of Ce5.6Sm0.4MoO15-delta (1.002 eV).

Preparation and Electrical Properties of New Oxide Ion Conductors Ce6-xGdxMoO15-delta (0.0 <= x <= 1.8)

A series of oxide ion conductors Ce6-xGdxMoO15-delta (0.0 <= x <= 1.8) have been prepared by the sol-gel method. Their properties were characterized by differential thermal analysis/thermogravimetry (DTA/TG), X-ray diffraction (XRD), Raman, IR, X-ray photoelectron spectroscopy (XPS), and AC impedance spectroscopy. The XRD patterns showed that the materials were single phase with a cubic fluorite structure. The conductivity of Ce6-xGdxMoO15-delta increases as x increases and reaches the maximum at x = 0.15. The conductivity of Ce4.5Gd1.5MoO15-delta is sigma(t) = 3.6 x 10(-3) S/cm at 700 degrees C, which is higher than that of Ce4.5/6Gd1.5/6O2-delta (sigma(t) = 2.6 x 10(-3) S/cm), and the corresponding activation energy of Ce4.5Gd1.5MoO15-delta (0.92 eV) is lower than that of Ce4.5/6Gd1.5/6O2-delta (1.18 eV).

Observation of Associated Near-Side and Away-Side Long-Range Correlations in √sNN=5.02 TeV Proton-Lead Collisions with the ATLAS Detector

Two-particle correlations in relative azimuthal angle (Delta phi) and pseudorapidity (Delta eta) are measured in root S-NN = 5.02 TeV p + Pb collisions using the ATLAS detector at the LHC. The measurements are performed using approximately 1 mu b(-1) of data as a function of transverse momentum (p(T)) and the transverse energy (Sigma E-T(Pb)) summed over 3.1 < eta < 4.9 in the direction of the Pb beam. The correlation function, constructed from charged particles, exhibits a long-range (2 < vertical bar Delta eta vertical bar < 5) "near-side" (Delta phi similar to 0) correlation that grows rapidly with increasing Sigma E-T(Pb). A long-range "away-side" (Delta phi similar to pi) correlation, obtained by subtracting the expected contributions from recoiling dijets and other sources estimated using events with small Sigma E-T(Pb), is found to match the near-side correlation in magnitude, shape (in Delta eta and Delta phi) and Sigma E-T(Pb) dependence. The resultant Delta phi correlation is approximately symmetric about pi/2, and is consistent with a dominant cos2 Delta phi modulation for all Sigma E-T(Pb) ranges and particle p(T).

Sigma signs.

Description based on: 1983-1984.

Dynamic strain ageing in Ni-base superalloy 720Li

An experimental investigation into the dynamic strain ageing (DSA) of a wrought Ni-base superalloy 720Li was conducted. Characteristics of jerky, flow have been studied at intermediate temperatures of 350, 400 and 450 degrees C at strain-rates between 10(-3) and 10(-5) s(-1). Serrations of Type C are predominant within the temperature/strain-rate range explored. The major characteristics of the serrations-i.e. (a) critical plastic strain for onset of serrations, epsilon(c); (b) average stress decrement, Delta sigma(avg); and (c) strain increment between serrations. Delta epsilon(BS)-have been examined at selected temperatures and strain-rates. Negative strain-rate sensitivity was observed in the DSA regime. However. temperature did not influence tensile properties such as yield strength, ultimate strength. elongation, reduction in area, and work hardening rate or fracture features in DSA regime. Analysis of the results Suggests that locking of the mobile dislocations by substitutional alloying elements is responsible for the DSA in alloy 720Li.

A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy

A CMOS gas sensor array platform with digital read-out containing 27 sensor pixels and a reference pixel is presented. A signal conditioning circuit at each pixel includes digitally programmable gain stages for sensor signal amplification followed by a second order continuous time delta sigma modulator for digitization. Each sensor pixel can be functionalized with a distinct sensing material that facilitates transduction based on impedance change. Impedance spectrum (up to 10 KHz) of the sensor is obtained off-chip by computing the fast Fourier transform of sensor and reference pixel outputs. The reference pixel also compensates for the phase shift introduced by the signal processing circuits. The chip also contains a temperature sensor with digital readout for ambient temperature measurement. A sensor pixel is functionalized with polycarbazole conducting polymer for sensing volatile organic gases and measurement results are presented. The chip is fabricated in a 0.35 CMOS technology and requires a single step post processing for functionalization. It consumes 57 mW from a 3.3 V supply.

Tuning photoinduced terahertz conductivity in monolayer graphene: Optical-pump terahertz-probe spectroscopy

Optical-pump terahertz-probe differential transmission measurements of as-prepared single layer graphene (AG) (unintentionally hole dopedwith Fermi energy E-F at similar to -180 meV), nitrogen doping compensated graphene (NDG) with E-F similar to -10 meV, and thermally annealed doped graphene (TAG) are examined quantitatively to understand the opposite signs of photoinduced dynamic terahertz conductivity Delta sigma. It is negative for AG and TAG but positive for NDG. We show that the recently proposed mechanism of multiple generations of secondary hot carriers due to Coulomb interaction of photoexcited carriers with the existing carriers together with the intraband scattering can explain the change of photoinduced conductivity sign and its magnitude. We give a quantitative estimate of Delta sigma in terms of controlling parameters-the Fermi energy E-F and momentum relaxation time tau. Furthermore, the cooling of photoexcited carriers is analyzed using a supercollision model which involves a defect mediated collision of the hot carriers with the acoustic phonons, thus giving an estimate of the deformation potential.