Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

Generating Circuit Tests by Exploiting Designed Behavior

This thesis describes two programs for generating tests for digital circuits that exploit several kinds of expert knowledge not used by previous approaches. First, many test generation problems can be solved efficiently using operation relations, a novel representation of circuit behavior that connects internal component operations with directly executable circuit operations. Operation relations can be computed efficiently by searching traces of simulated circuit behavior. Second, experts write test programs rather than test vectors because programs are more readable and compact. Test programs can be constructed automatically by merging program fragments using expert-supplied goal-refinement rules and domain-independent planning techniques.

Filtragem digital e reconstrução de sinais em frequência intermediária usando FPGA

O presente trabalho trata da filtragem e reconstrução de sinais em frequência intermediária usando FPGA. É feito o desenvolvimento de algoritmos usando processamento digital de sinais e também a implementação dos mesmos, constando desde o projeto da placa de circuito impresso, montagem e teste. O texto apresenta um breve estudo de amostragem e reconstrução de sinais em geral. Especial atenção é dada à amostragem de sinais banda-passante e à análise de questões práticas de reconstrução de sinais em frequência intermediária. Dois sistemas de reconstrução de sinais baseados em processamento digital de sinais, mais especificamente reamostragem no domínio discreto, são apresentados e analisados. São também descritas teorias de processos de montagem e soldagem de placas eletrônicas com objetivo de definir uma metodologia de projeto, montagem e soldagem de placas eletrônicas. Tal metodologia é aplicada no projeto e manufatura do protótipo de um módulo de filtragem digital para repetidores de telefonia celular. O projeto, implementado usando FPGA, é baseado nos dois sistemas supracitados. Ao final do texto, resultados obtidos em experimentos de filtragem digital e reconstrução de sinais em frequência intermediária com o protótipo desenvolvido são apresentados.

A radial basis function network (RBFN) for function approximation

A radial basis function network (RBFN) circuit for function approximation is presented. Simulation and experimental results show that the network has good approximation capabilities. The RBFN was a squared hyperbolic secant with three adjustable parameters amplitude, width and center. To test the network a sinusoidal and sine function,vas approximated.

An analog implementation of radial basis function network appropriate for transducer linearizer

A circuit for transducer linearizer tasks have been designed and built using discrete components and it implements by: a Radial Basis Function Network (RBFN) with three basis functions. The application in a linearized thermistor showed that the network has good approximation capabilities. The circuit advantages is the amplitude, width and center.

A heuristic algorithm to generate test program sequences for moving probe electronic test equipment

The electronics industry, is experiencing two trends one of which is the drive towards miniaturization of electronic products. The in-circuit testing predominantly used for continuity testing of printed circuit boards (PCB) can no longer meet the demands of smaller size circuits. This has lead to the development of moving probe testing equipment. Moving Probe Test opens up the opportunity to test PCBs where the test points are on a small pitch (distance between points). However, since the test uses probes that move sequentially to perform the test, the total test time is much greater than traditional in-circuit test. While significant effort has concentrated on the equipment design and development, little work has examined algorithms for efficient test sequencing. The test sequence has the greatest impact on total test time, which will determine the production cycle time of the product. Minimizing total test time is a NP-hard problem similar to the traveling salesman problem, except with two traveling salesmen that must coordinate their movements. The main goal of this thesis was to develop a heuristic algorithm to minimize the Flying Probe test time and evaluate the algorithm against a "Nearest Neighbor" algorithm. The algorithm was implemented with Visual Basic and MS Access database. The algorithm was evaluated with actual PCB test data taken from Industry. A statistical analysis with 95% C.C. was performed to test the hypothesis that the proposed algorithm finds a sequence which has a total test time less than the total test time found by the "Nearest Neighbor" approach. Findings demonstrated that the proposed heuristic algorithm reduces the total test time of the test and, therefore, production cycle time can be reduced through proper sequencing.

Iowa improved driver licensing procedures demonstration project; closed circuit color television electro-mechanical teaching/testing licensing system. Final report.

National Highway Traffic Safety Administration, Washington, D.C.

Development of diagnostic and prognostic algorithms from vacuum circuit breaker restrike review and its validation proposal

The CIGRE WGs A3.20 and A3.24 identify the requirements of simulation tools to predict various stresses during the development and operational phases of medium voltage vacuum circuit breaker (VCB) testing. This paper reviews the modelling methodology [13], VCB models and tools to identify future research. It will include the application of the VCB model for the impending failure of a VCB using electro-magnetic-transient-program with diagnostic and prognostic algorithm development. The methodology developed for a VCB degradation model is to modify the dielectric equation to cover a restriking period of more than 1 millimetre.

Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification or Cur is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit fly some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits

Abstract—A method of testing for parametric faults of analog circuits based on a polynomial representaion of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies apart from DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. The method needs very little augmentation of circuit to make it testable as only output parameters are used for classification. This procedure is shown to uncover several parametric faults causing smaller than 5 % deviations the nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is also proposed.

Design, Construction and Testing of a Hydraulic Power Take-Off for Wave Energy Converters

This paper presents the construction, mathematical modeling and testing of a scaled universal hydraulic Power Take-Off (PTO) device for Wave Energy Converters (WECs). A specific prototype and test bench were designed and built to carry out the tests. The results obtained from these tests were used to adjust an in-house mathematical model. The PTO was initially designed to be coupled to a scaled wave energy capture device with a low speed and high torque oscillating motion and high power fluctuations. Any Energy Capture Device (ECD) that fulfils these requirements can be coupled to this PTO, provided that its scale is adequately defined depending on the rated power of the full scale prototype. The initial calibration included estimation of the pressure drops in the different components, the pressurization time of the oil inside the hydraulic cylinders and the volumetric efficiency of the complete circuit. Since the overall efficiency measured during the tests ranged from 0.69 to 0.8 and the dynamic performance of the PTO was satisfactory, the results are really promising and it is believed that this solution might prove effective in real devices.

Fabrication and testing of a high resolution extensometer based on resonant MEMS strain sensors

A novel type of linear extensometer with exceptionally high resolution of 4 nm based on MEMS resonant strain sensors bonded on steel and operating in a vacuum package is presented. The tool is implemented by means of a steel thin bar that can be pre-stressed in tension within two fixing anchors. The extension of the bar is detected by using two vacuum-packaged resonant MEMS double- ended tuning fork (DETF) sensors bonded on the bar with epoxy glue, one of which is utilized for temperature compensation. Both sensors are driven by a closed loop self-oscillating transresistance amplifier feedback scheme implemented on a PCB (Printed Circuit Board). On the same board, a microcontroller-based frequency measurement circuit is also implemented, which is able to count the square wave fronts of the MEMS oscillator output with a resolution of 20 nsec. The system provides a frequency noise of 0.2 Hz corresponding to an extension resolution of 4 nm for the extensometer. Nearly perfect temperature compensation of the frequency output is achieved in the temperature range 20-35 C using the reference sensor. © 2011 IEEE.

Reversible disconnection of the hippocampal-prelimbic cortical circuit impairs spatial learning but not passive avoidance learning in rats

Wistar rats, treated with the GABA(A) receptor agonist muscimol, were used to investigate the role of the hippocampal-prelimbic cortical (Hip-PLC) circuit in spatial learning in the Morris water maze task, and in passive avoidance learning in the step-thr

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.