Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop

In this paper, two new dual-path based area efficient loop filtercircuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 CSM analog process with 1.8V supply. The proposed circuits achievedup to 85% savings in capacitor area. Simulations showed goodmatch of the new circuits with the conventional circuit. Theproposed circuits are particularly useful in applications thatdemand low die area.

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.

Statistics of an adiabatic charge pump

We investigate the effect of time-dependent cyclic-adiabatic driving on the charge transport in a quantum junction. We propose a nonequilibrium Green's function formalism to study the statistics of the charge pumped (at zero bias) through the junction. The formulation is used to demonstrate charge pumping in a single electronic level coupled to two (electronic) reservoirs with time-dependent couplings. An analytical expression for the average pumped current for a general cyclic driving is derived. It is found that for zero bias, for a certain class of driving, the Berry phase contributes only to the odd cumulants. In contrast, a quantum master equation formulation does not show a Berry-phase effect at all.

A study on the realization of radio frequency energy AC/DC charge pump based on MOS FET

This paper presents a novel efficient charge pump composed of low Vth metal-oxide-semiconductor (MOS) field effect transistors (FET) in the course of realizing radio frequency (RF) energy AC/DC conversion. The novel structure eliminates those defects caused by typical Schottky-diode charge pumps, which are dependent on specific processes and inconsistent in quality between different product batches. Our analyses indicate that an easy-fabricated, stable and efficient RF energy AC/DC charge pump can be conveniently implemented through reasonably configuring the MOS transistor aspect ratio, and other design parameters such as capacitance, multiplying stages to meet various demands on performance.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

A novel low-power input-independent MOS AC/DC charge pump

This paper presents a novel fully integrated MOS AC to DC charge pump with low power dissipation and stable output for RFID applications. To improve the input sensitivity, we replaced Schottky-diodes in conventional charge pumps with MOS diodes with zero threshold, which has less process defects and is thus more compatible with other circuits. The charge pump in a RFID transponder is implemented in a 0.35um CMOS technology with 0.24 sq mm die size. The analytical model of the charge pump and the simulation results are presented.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

Analisi dinamica e a regime del convertitore Dickson-Charge-Pump

I circuti di tipo charge-pump trovano vasto impiego nell'elettronica moderna in quanto offrono un metodo semplice e totalmente integrato per elevare le basse tensioni di alimentazione tipiche dei circuiti digitali e trasformarle nelle alimentazioni adatte al pilotaggio di circuti di programmazione delle memorie, al pilotaggio dei mos di potenza, alla generazione della tensione di riferimento dei VCO nei PLL e in numerose altre applicazioni. Questa tesi studia il circuito charge-pump di Dickson nel suo comportamento sia a regime stazionario sia a regime dinamico. Al fine di aumentare l'efficienza è infatti importante attivare il circuito solo all'occorrenza, prestando attenzione al transitorio di accensione. Ogni aspetto teorico viene verificato per mezzo di simulazioni su LTSpice. Si è quindi potuto constatare che un dimensionamento corretto del numero di stadi ottimizza le prestazioni sia statiche che dinamiche sotto il vincolo di una massima occupazione d'area. L'impiego dei circuiti charge-pump si prevede possa essere sempre più diffuso in futuro, visto il trend verso un maggiore livello di integrazione dei sistemi elettronici e la tendenza ad utilizzare tensioni di alimentazione sempre più basse.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.