62 resultados para Vex assembler


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Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores

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"Supported in part by contract AT(11-1)-2118 with the United States Atomic Energy Commission."

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Issued also as thesis (M.S.) University of Illinois.

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Thesis (M. S.)--University of Illinois at Urbana-Champaign.

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Thesis (M. S.)--University of Illinois at Urbana-Champaign.

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"December 1, 1969."

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Mode of access: Internet.

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Timinganalysis of assembler code is essential to achieve the strongest possible guarantee of correctness for safety-critical, real-time software. Previous work has shown how timingconstrain ts on controlflow paths through high-level language programs can be formalised using the semantics of the statements comprisingthe path. We extend these results to assembler-level code where it becomes possible to not only determine timingconstrain ts, but also to verify them against the known execution times for each instruction. A minimal formal model is developed with both a weakest liberal precondition and a strongest postcondition semantics. However, despite the formalism’s simplicity, it is shown that complex timingb ehaviour associated with instruction pipeliningand iterative code can be modelled accurately.

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Previous work on formally modelling and analysing program compilation has shown the need for a simple and expressive semantics for assembler level programs. Assembler programs contain unstructured jumps and previous formalisms have modelled these by using continuations, or by embedding the program in an explicit emulator. We propose a simpler approach, which uses techniques from compiler theory in a formal setting. This approach is based on an interpretation of programs as collections of program paths, each of which has a weakest liberal precondition semantics. We then demonstrate, by example, how we can use this formalism to justify the compilation of block-structured high-level language programs into assembler.

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Mycoplasma suis, the causative agent of porcine infectious anemia, has never been cultured in vitro and mechanisms by which it causes disease are poorly understood. Thus, the objective herein was to use whole genome sequencing and analysis of M. suis to define pathogenicity mechanisms and biochemical pathways. M. suis was harvested from the blood of an experimentally infected pig. Following DNA extraction and construction of a paired end library, whole-genome sequencing was performed using GS-FLX (454) and Titanium chemistry. Reads on paired-end constructs were assembled using GS De Novo Assembler and gaps closed by primer walking; assembly was validated by PFGE. Glimmer and Manatee Annotation Engine were used to predict and annotate protein-coding sequences (CDS). The M. suis genome consists of a single, 742,431 bp chromosome with low G+C content of 31.1%. A total of 844 CDS, 3 single copies, unlinked rRNA genes and 32 tRNAs were identified. Gene homologies and GC skew graph show that M. suis has a typical Mollicutes oriC. The predicted metabolic pathway is concise, showing evidence of adaptation to blood environment. M. suis is a glycolytic species, obtaining energy through sugars fermentation and ATP-synthase. The pentose-phosphate pathway, metabolism of cofactors and vitamins, pyruvate dehydrogenase and NAD(+) kinase are missing. Thus, ribose, NADH, NADPH and coenzyme A are possibly essential for its growth. M. suis can generate purines from hypoxanthine, which is secreted by RBCs, and cytidine nucleotides from uracil. Toxins orthologs were not identified. We suggest that M. suis may cause disease by scavenging and competing for host nutrients, leading to decreased life-span of RBCs. In summary, genome analysis shows that M. suis is dependent on host cell metabolism and this characteristic is likely to be linked to its pathogenicity. The prediction of essential nutrients will aid the development of in vitro cultivation systems.

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Program compilation can be formally defined as a sequence of equivalence-preserving transformations, or refinements, from high-level language programs to assembler code, Recent models also incorporate timing properties, but the resulting formalisms are intimidatingly complex. Here we take advantage of a new, simple model of real-time refinement, based on predicate transformer semantics, to present a straightforward compilation formalism that incorporates real-time constraints. (C) 2002 Elsevier Science B.V. All rights reserved.

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O desenvolvimento do processo de produção de um produto para a indústria automóvel é sempre um desafio de nível de dificuldade exigente. Este trabalho teve por base o estudo do desenvolvimento do processo de produção de um produto para a área automóvel, constituído por diversos componentes e exigindo diversas etapas de produção. O desafio partiu de um cliente da SIMOLDES - PLÁSTICOS, S.A. que necessitava de uma peça em plástico para um novo modelo de automóvel. Foram estabelecidas as condições iniciais impostas pelo cliente e foram estudados os condicionalismos impostos pelas mesmas. Foram estudadas diferentes alternativas com vista à optimização do processo, garantindo a qualidade e tentando minimizar o custo final do produto. Foi realizada uma optimização dos moldes, por forma a poderem ser utilizadas máquinas com Força de Fecho mais baixa. Foram desenvolvidos alguns equipamentos que permitiram à empresa optar por novas formas de produção, utilizando materiais mais amigos do ambiente. Foram estudadas as condições de distribuição e optimização das tarefas, com vista à garantia do cumprimento dos prazos de entrega exigidos pelo cliente. Foi estudado o ‘layout’ que optimizou as operações de transporte das diferentes peças que constituem o produto final. Este trabalho foi elaborado com base num trabalho desenvolvido e implementado na SIMOLDES – PLÁSTICOS, S.A.

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Advances in computer memory technology justify research towards new and different views on computer organization. This paper proposes a novel memory-centric computing architecture with the goal to merge memory and processing elements in order to provide better conditions for parallelization and performance. The paper introduces the architectural concepts and afterwards shows the design and implementation of a corresponding assembler and simulator.