An optimization-based algorithm for shunt active filter under distorted supply voltages

When the supply voltages are balanced and sinusoidal, load compensation can give both unity power factor (UPF) and perfect harmonic cancellation (PHC) source currents. But under distorted supply voltages, achieving both UPF and PHC currents are not possible and contradictory to each other. Hence there should be an optimal performance between these two important compensation goals. This paper presents an optimal control algorithm for load compensation under unbalanced and distorted supply voltages. In this algorithm source currents are compensated for reactive, imbalance components and harmonic distortions set by the limits. By satisfying the harmonic distortion limits and power balance, this algorithm gives the source currents which will provide the maximum achievable power factor. The detailed simulation results using MATLAB are presented to support the performance of the proposed optimal control algorithm.

INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations

Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters. Hence these models are hard to use directly to make high level microarchitectural trade-offs in the initial exploration phase of a design. In this paper, we propose INTACTE, a tool that can be used by architects toget reasonably accurate interconnect area, delay, and power estimates based on a few architecture level parameters for the interconnect such as length, width (in number of bits), frequency, and latency for a specified technology and voltage. The tool uses well known models of interconnect delay and energy taking into account the wire pitch, repeater size, and spacing for a range of voltages and technologies.It then solves an optimization problem of finding the lowest energy interconnect design in terms of the low level circuit parameters, which meets the architectural constraintsgiven as inputs. In addition, the tool also provides the area, energy, and delay for a range of supply voltages and degrees of pipelining, which can be used for micro-architectural exploration of a chip. The delay and energy models used by the tool have been validated against low level circuit simulations. We discuss several potential applications of the tool and present an example of optimizing interconnect design in the context of clustered VLIW architectures. Copyright 2007 ACM.

Flexible Phynox Alloy with Integrated Piezoelectric Thin Film for Micro Actuation Application

In this paper, we report on the application aspect of piezoelectric ZnO thin film deposited on flexible phynox alloy substrate. Highly crystalline piezoelectric ZnO thin films were deposited by RF reactive magnetron sputtering and were characterized by XRD, SEM, AFM analysis. Also, the effective d(33) coefficient value measurement was performed. The actuator element is a circular diaphragm of phynox alloy on to which piezoelectric ZnO thin film was deposited. ZnO film deposited actuator element was firmly fixed inside a suitable concave perspex mounting designed specifically for micro actuation purpose. The actuator element was excited at different frequencies for the supply voltages of 2V, 5V and 8V. Maximum deflection of the ZnO film deposited diaphragm was measured to be 1.25 mu m at 100 Hz for the supply voltage of 8V. The developed micro actuator has the potential to be used as a micro pump for pumping nano liters to micro liters of fluids per minute for numerous biomedical and aerospace applications.

Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems

This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.

Optical-Phonon-Limited High-Field Transport in Layered Materials

An optical-phonon-limited velocity model has been employed to investigate high-field transport in a selection of layered 2-D materials for both, low-power logic switches with scaled supply voltages, and high-power, high-frequency transistors. Drain currents, effective electron velocities, and intrinsic cutoff frequencies as a function of carrier density have been predicted, thus providing a benchmark for the optical-phonon-limited high-field performance limits of these materials. The optical-phonon-limited carrier velocities for a selection of multi-layers of transition metal dichalcogenides and black phosphorus are found to be modest compared to their n-channel silicon counterparts, questioning the utility of biasing these devices in the source-injection dominated regime. h-BN, at the other end of the spectrum, is shown to be a very promising material for high-frequency, high-power devices, subject to the experimental realization of high carrier densities, primarily due to its large optical-phonon energy. Experimentally extracted saturation velocities from few-layer MoS2 devices show reasonable qualitative and quantitative agreement with the predicted values. The temperature dependence of the measured v(sat) is discussed and compared with the theoretically predicted dependence over a range of temperatures.

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the power consumption of the cell. This shaped wordline pulse results in improved read noise margin without any degradation in access time for small wordline load. The improvement is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time (depending on the size of boosting capacitance), wordline voltage becomes negative and charges up to zero after a specific time that results in a lower leakage current compared to conventional SRAM. The proposed technique results in at least 2× improvement in read noise margin while it improves write margin by 3× for lower supply voltages than 0.7 V. The leakage power for the proposed SRAM is reduced by 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The main advantage of the proposed wordline driver is the improvement of dynamic noise margin with less than 2.5% penalty in area. TSMC 65 nm technology models are used for simulations.

Nonlinear behavioral modeling of mixed signal RF-digital I/O devices

Esta tese investiga a caracterização (e modelação) de dispositivos que realizam o interface entre os domínios digital e analógico, tal como os buffers de saída dos circuitos integrados (CI). Os terminais sem fios da atualidade estão a ser desenvolvidos tendo em vista o conceito de rádio-definido-por-software introduzido por Mitola. Idealmente esta arquitetura tira partido de poderosos processadores e estende a operação dos blocos digitais o mais próximo possível da antena. Neste sentido, não é de estranhar que haja uma crescente preocupação, no seio da comunidade científica, relativamente à caracterização dos blocos que fazem o interface entre os domínios analógico e digital, sendo os conversores digital-analógico e analógico-digital dois bons exemplos destes circuitos. Dentro dos circuitos digitais de alta velocidade, tais como as memórias Flash, um papel semelhante é desempenhado pelos buffers de saída. Estes realizam o interface entre o domínio digital (núcleo lógico) e o domínio analógico (encapsulamento dos CI e parasitas associados às linhas de transmissão), determinando a integridade do sinal transmitido. Por forma a acelerar a análise de integridade do sinal, aquando do projeto de um CI, é fundamental ter modelos que são simultaneamente eficientes (em termos computacionais) e precisos. Tipicamente a extração/validação dos modelos para buffers de saída é feita usando dados obtidos da simulação de um modelo detalhado (ao nível do transístor) ou a partir de resultados experimentais. A última abordagem não envolve problemas de propriedade intelectual; contudo é raramente mencionada na literatura referente à caracterização de buffers de saída. Neste sentido, esta tese de Doutoramento foca-se no desenvolvimento de uma nova configuração de medição para a caracterização e modelação de buffers de saída de alta velocidade, com a natural extensão aos dispositivos amplificadores comutados RF-CMOS. Tendo por base um procedimento experimental bem definido, um modelo estado-da-arte é extraído e validado. A configuração de medição desenvolvida aborda não apenas a integridade dos sinais de saída mas também do barramento de alimentação. Por forma a determinar a sensibilidade das quantias estimadas (tensão e corrente) aos erros presentes nas diversas variáveis associadas ao procedimento experimental, uma análise de incerteza é também apresentada.

Hardware implementation of type-2 programmable fuzzifier

The design of full programmable type-2 membership function circuit is presented in this paper. This circuit is used to implement the fuzzifier block of Type-2 Fuzzy Logic Controller chip. In this paper the type-2 fuzzy set was obtained by blurring the width of the type-1 fuzzy set. This circuit allows programming the height and the shape of the membership function. It operates in current mode, with supply voltage of 3.3V. The simulation results of interval type-2 membership function circuit have been done in CMOS 0.35μm technology using Mentor Graphics software. © 2011 IEEE.

Application of Conservative Power Theory to load and line characterization and revenue metering

This paper proposes a set of performance factors for load characterization and revenue metering. They are based on the Conservative Power Theory, and each of them relates to a specific load non-ideality (unbalance, reactivity, distortion). The performance factors are capable to characterize the load under different operating conditions, considering also the effect of non-negligible line impedances and supply voltage deterioration. © 2012 IEEE.

Teorias de potência conservativa e instantânea: análise comparativa

Pós-graduação em Engenharia Elétrica - FEB

Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the threshold and supply voltages scaling, increasing the power density and creating local thermal issues, such as hot spots, thermal runaway and thermal cycles. In addiction, the introduction of new materials and the smaller devices dimension are reducing transistors robustness, that combined with high temperature and frequently thermal cycles, are speeding up wear out processes. Those effects are no longer addressable only at the process level. Consequently the deep sub-micron devices will require solutions which will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to introduce logic and system able to cope with the yield and reliability loss. The ITRS roadmap suggests the following research steps to integrate the design for manufacturability and reliability in the standard CAD automated design flow: i) The implementation of new analysis algorithms able to predict the system thermal behavior with the impact to the power and speed performances. ii) High level wear out models able to predict the mean time to failure of the system (MTTF). iii) Statistical performance analysis able to predict the impact of the process variation, both random and systematic. The new analysis tools have to be developed beside new logic and system strategies to cope with the future challenges, as for instance: i) Thermal management strategy that increase the reliability and life time of the devices acting to some tunable parameter,such as supply voltage or body bias. ii) Error detection logic able to interact with compensation techniques as Adaptive Supply Voltage ASV, Adaptive Body Bias ABB and error recovering, in order to increase yield and reliability. iii) architectures that are fundamentally resistant to variability, including locally asynchronous designs, redundancy, and error correcting signal encodings (ECC). The literature already features works addressing the prediction of the MTTF, papers focusing on thermal management in the general purpose chip, and publications on statistical performance analysis. In my Phd research activity, I investigated the need for thermal management in future embedded low-power Network On Chip (NoC) devices.I developed a thermal analysis library, that has been integrated in a NoC cycle accurate simulator and in a FPGA based NoC simulator. The results have shown that an accurate layout distribution can avoid the onset of hot-spot in a NoC chip. Furthermore the application of thermal management can reduce temperature and number of thermal cycles, increasing the systemreliability. Therefore the thesis advocates the need to integrate a thermal analysis in the first design stages for embedded NoC design. Later on, I focused my research in the development of statistical process variation analysis tool that is able to address both random and systematic variations. The tool was used to analyze the impact of self-timed asynchronous logic stages in an embedded microprocessor. As results we confirmed the capability of self-timed logic to increase the manufacturability and reliability. Furthermore we used the tool to investigate the suitability of low-swing techniques in the NoC system communication under process variations. In this case We discovered the superior robustness to systematic process variation of low-swing links, which shows a good response to compensation technique as ASV and ABB. Hence low-swing is a good alternative to the standard CMOS communication for power, speed, reliability and manufacturability. In summary my work proves the advantage of integrating a statistical process variation analysis tool in the first stages of the design flow.

A proposed bare-tether experiment on board a sounding rocket

A mission on board a sounding rocket to carry out two bare-tether experiments is proposed: a test of orbital-motion-limited (OML) collection and the proof-of-flight of a technique to determine the (neutral) density vertical profile in the critical E-layer. Since full bias from the motional field will be small (~ 20V), corresponding to a tape 1 km long and V rocket <8 km/s, a power source with a range of supply voltages of few kV would be used. First, the negative terminal of the supply would be connected to the tape, and the positive terminal to a round, conductive boom of length 10 - 20 m; electrons collected by the boom cross the supply into the tape, where they leak out at the rate of ion impact plus secondary emission. Determination of the density profile from measurements of auroral emissions observed from the rocket, as secondaries racing down the magnetic field reach an E-layer footprint, are discussed. Next the positive terminal of the voltage supply is connected to the tape, and the negative terminal to a Hollow Cathode (HC); electrons now collected by the tape cross the supply, and are ejected at the HC. The opposite connections, with current collection operated by tape and boom, and operating on electrons and ions, and through partial switching in the supply, allow testing OML collection in almost all respects it depends on.

Modelling, simulation and validation of a twelve-pulse autotransformer rectifier for aerospace applications

A microcap SPICE circuit-level model of a 12-pulse autotransformer based rectifier for an aircraft fuel-pump motor drive is described. The importance of including the nonlinear magnetising inductance of the interphase transformers is illustrated. Small supply voltage distortions are seen to result in current imbalance in the interphase transformers, degrading the rectifier input current, and may lead to infringement of the power quality specification. The model has been validated for various operating supply voltages, frequencies and output powers, against measurements from a 3.75 kW unit.

High-Performance WSe2 CMOS Technology and Integrated Circuits.

Because of their extraordinary structural and electrical properties, two dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (~38) and small static power (Pico-Watts), paving the way for low power electronic system in 2D materials.