Memòria de recerca: paral·lelització dels diccionaris de la Standard Template Library de C++

Estudi elaborat a partir d’una estada a la Universität Karlsruhe entre gener i maig del 2007. Les biblioteques d’estructures de dades defineixen interfícies i implementen algorismes i estructures de dades fonamentals. Un exemple n’és la Satandard Template Library (STL ), que forma part del llenguatge de programació C++. En el marc d’una tesi, s’està treballant per obtenir implementacions més eficients i/o versàtils d’alguns components de la STL. Per a fer-ho s’utilitzen tècniques de la enginyeria d’algorismes. En particular, s’integra el coneixement de la comunitat algorítmica i es té en consideració la tecnologia existent. L’acció durant l’estada s’ha emmarcat en el desenvolupament la Multi Core STL (MCSTL ). La MCSTL és una implementació paral•lela de la STL per a màquines multi-core. Les màquines multi-core són actualment l’únic tipus de màquina disponible al mercat. Per tant, tot i que el paral•lelisme obtingut no sigui òptim, és preferible a tenir els processadors esperant, ja que , la tendència és que el nombre de processadors per computador augmenti.

Findings of the standard benchmark library study group /

Includes bibliographical references.

An Adaptive Quadrilateral Mesh in Curved Domains

An nonlinear elliptic system for generating adaptive quadrilateral meshes in curved domains is presented. The presented technique has been implemented in the C++ language with the help of the standard template library. The software package writes the converged meshes in the GMV and the Matlab formats. Grid generation is the first very important step for numerically solving partial differential equations. Thus, the presented C++ grid generator is extremely important to the computational science community.

Uma Introdução à Sintaxe do C++: C++03 e C++11

A interacção dos humanos com os computadores envolve uma combinação das tarefas de programação e de utilização. Nem sempre é explícita a diferença entre as duas tarefas. Introduzir comandos num programa de desenho assistido por computador é utilização ou programação numa linguagem interpretada? Modificar uma folha de cálculo com macros é utilização ou programação? Usar um “Integrated Development Environment” ou IDE para inserir dados num ficheiro é utilização (do IDE) ou programação? A escrita de um texto usando LaTeX ou HTML é utilização ou programação numa “markup language”? Recorrer a um programa de computação simbólica é utilização ou programação? Utilizar um processador de texto é utilização ou programação visual? Ao utilizador não se exige um conhecimento completo de todos os comandos, todos os menus, todos os símbolos do software que utiliza. Nem a memorização da sintaxe e de todos os pormenores de funcionamento de um programa é um atributo necessário ou sequer útil ao utilizador; a concretização desse conhecimento não assegura maior eficiência na utilização. Quando se começa, apenas algumas instruções elementares são recebidas, por vezes de um colega, de um Professor, ou obtidas recorrendo à pesquisa na Internet. Com a familiarização, o utilizador exige mais do Software que usa e de si próprio: um manual passa a ser um recurso de grande utilidade. A confiança conquistada gera, periodicamente, a necessidade de auto-exame e de aumento do âmbito do conhecimento. Desta forma, quem utiliza computadores acaba por ser confrontado com uma tarefa que, efectivamente, pode ser considerada ou requer programação. Põe-se uma questão no imediato (se ninguém decidiu por si) que é a da selecção da linguagem de programação. A abordagem multiparadigma e longa experiência de utilização do C++ tornam-no atractivo para aplicações onde a eficiência se combina com a disponibilidade de estruturas de dados e algoritmos adoptados pela indústria (o que coloquialmente se denomina STL, Standard Template Library, cf. [#breymann, #josuttis], mais geralmente biblioteca Standard). Adicionalmente, linguagens populares como o Java, C# e PHP possuem sintaxes inspiradas e em muitas partes coincidentes com as do C e C++. Por exemplo, um ciclo “for” em Java é parcialmente coincidente com o do C99, que é um sub-conjunto do “for” do C++. São os pormenores, a eficiência e as capacidades do C++ que permitem a criação de software Profissional. Todos os sistemas operativos clássicos (Unix, Microsoft Windows, Linux) dispõem de compiladores, IDE, bibliotecas e são em grande parte construídos recorrendo a C e C++. Relativamente a outras linguagens, a quantidade de ferramentas disponível e o conhecimento adquirido durante décadas é difícil de ignorar. Esse conhecimento faz com que a sintaxe do C++ pareça muito maior do que o estritamente necessário e afaste potenciais interessados. A longa evolução do C++ introduziu também uma diferença no estilo muito marcada. Código dos anos 80 e 90 do século XX é frequentemente menos legível do que o que correntemente se produz. Muitos tutoriais disponíveis online fazem parecer a linguagem menos rigorosa (e mais complexa) do que na realidade é, já que raramente é apresentado o caso geral da sintaxe. Constata-se que muitos autores ainda usam os cabeçalhos do C, quando já não são necessários. Scott Meyers afirma que o C++ é uma federação de linguagens [#scottmeyers] e por esse facto requer perspectivas de abordagem distintas de outras linguagens. Sem alguma sistematização é difícil apreciar a sua compacidade e coerência. Porém, a forma harmoniosa como as componentes sintácticas se encaixam é uma grande mais-valia do C++ só constatada com experimentação e leitura atenta. A presente monografia dirige-se a quem pretenda utilizar o C++ como ferramenta profissional de Software. Em termos de pré-requisitos Académicos, dir-se-á que um curso (1º Ciclo) de Ciência ou de Engenharia aumentará o interesse por certos aspectos mais técnicos da linguagem mas qualquer indivíduo com gosto pela experimentação tirará proveito do conteúdo. Este texto não busca a exaustividade enciclopédica na cobertura do tema. Neste texto forneço, de forma directa, uma introdução ao C++ a qual permite começar a produzir código sem os custos da dispersão de fontes e notações na recolha de informação. Antecipo assim a sua utilização nos Países de Língua Portuguesa, uma vez que os textos que encontrei são ora mais exigentes ora menos completos, frequentemente ambos.

Millora en la creació i configuració automatitzada de dispositius a la xarxa lliure Guifi.net

Guifi.net es una red libre de telecomunicaciones construida a iniciativa de los propios participantes que, mediante un acuerdo entre iguales, se interconectan para compartir servicios y recursos. Del vínculo filosófico con el software libre deriva que toda la información sea pública, mientras que del agnosticismo tecnológico, la utilización de cualquier dispositivo del mercado. Por esto existe el 'unsolclic', una secuencia de órdenes de confi guración genérica de dispositivos y verdadero factor de éxito. El objetivo del proyecto es mejorar el proceso de incorporación de nuevos dispositivos a la aplicación actual. Mediante una nueva gestión web y un sistema de plantillas estándar, los usuarios avanzados podran crear los confi guradores 'unsolclic' para los nuevos dispositivos del mercado y mantener los existentes con más facilidad y eficiencia.

Role and extent of lymphadenectomy during radical cystectomy for invasive bladder cancer

There is substantial variability in the extent of the node dissection performed during radical cystectomy for bladder cancer. Here, we review the diagnostic assessment of lymph node metastasis and the prognostic and therapeutic benefit for pelvic node dissection for bladder cancer. A review of the applicable urologic literature regarding the topics of lymphadenectomy for bladder cancer was conducted. Nodal metastasis above a limited or standard template is not uncommon, with up to 16% of all nodal metastasis detected proximal to the aortic bifurcation. However, skip metastasis is extremely rare. Proteins associated purely with epithelial tissue such as cytokeratin (CK)-19, CK-20, and uroplakin II have been observed in reportedly negative nodal specimens, which indicates that routine microscopic analysis of nodal tissue may miss small foci of metastatic cancer. In addition to the surgical technique, the total number of lymph nodes removed is influenced by patient anatomy and pathologic processing and therefore may be unsuitable as a procedural quality statement. Consecutively, meticulous removal of tissue within a defined and uniformly applied template may be more relevant than absolute nodal count. Observational cohort series indicate an improved oncologic outcome for patients undergoing extensive nodal dissection. The results of two randomized controlled trials addressing the extent of nodal dissection for bladder cancer are forthcoming.

Valuing the Health States Associated with Chlamydia trachomatis Infections and Their Sequelae: A Systematic Review of Economic Evaluations and Primary Studies

OBJECTIVES Economic evaluations of interventions to prevent and control sexually transmitted infections such as Chlamydia trachomatis are increasingly required to present their outcomes in terms of quality-adjusted life-years using preference-based measurements of relevant health states. The objectives of this study were to critically evaluate how published cost-effectiveness studies have conceptualized and valued health states associated with chlamydia and to examine the primary evidence available to inform health state utility values (HSUVs). METHODS A systematic review was conducted, with searches of six electronic databases up to December 2012. Data on study characteristics, methods, and main results were extracted by using a standard template. RESULTS Nineteen economic evaluations of relevant interventions were included. Individual studies considered different health states and assigned different values and durations. Eleven studies cited the same source for HSUVs. Only five primary studies valued relevant health states. The methods and viewpoints adopted varied, and different values for health states were generated. CONCLUSIONS Limitations in the information available about HSUVs associated with chlamydia and its complications have implications for the robustness of economic evaluations in this area. None of the primary studies could be used without reservation to inform cost-effectiveness analyses in the United Kingdom. Future debate should consider appropriate methods for valuing health states for infectious diseases, because recommended approaches may not be suitable. Unless we adequately tackle the challenges associated with measuring and valuing health-related quality of life for patients with chlamydia and other infectious diseases, evaluating the cost-effectiveness of interventions in this area will remain problematic.

Area-delay Trade-offs of Texture Decompressors for a Graphics Processing Unit

Graphics Processing Units have become a booster for the microelectronics industry. However, due to intellectual property issues, there is a serious lack of information on implementation details of the hardware architecture that is behind GPUs. For instance, the way texture is handled and decompressed in a GPU to reduce bandwidth usage has never been dealt with in depth from a hardware point of view. This work addresses a comparative study on the hardware implementation of different texture decompression algorithms for both conventional (PCs and video game consoles) and mobile platforms. Circuit synthesis is performed targeting both a reconfigurable hardware platform and a 90nm standard cell library. Area-delay trade-offs have been extensively analyzed, which allows us to compare the complexity of decompressors and thus determine suitability of algorithms for systems with limited hardware resources.

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Institute songs /

"Standard musical library."

Fragilariopsis kerguelensis images from sediment core PS1768-8

Background: Light microscopic analysis of diatom frustules is widely used both in basic and applied research, notably taxonomy, morphometrics, water quality monitoring and paleo-environmental studies. In these applications, usually large numbers of frustules need to be identified and / or measured. Although there is a need for automation in these applications, and image processing and analysis methods supporting these tasks have previously been developed, they did not become widespread in diatom analysis. While methodological reports for a wide variety of methods for image segmentation, diatom identification and feature extraction are available, no single implementation combining a subset of these into a readily applicable workflow accessible to diatomists exists. Results: The newly developed tool SHERPA offers a versatile image processing workflow focused on the identification and measurement of object outlines, handling all steps from image segmentation over object identification to feature extraction, and providing interactive functions for reviewing and revising results. Special attention was given to ease of use, applicability to a broad range of data and problems, and supporting high throughput analyses with minimal manual intervention. Conclusions: Tested with several diatom datasets from different sources and of various compositions, SHERPA proved its ability to successfully analyze large amounts of diatom micrographs depicting a broad range of species. SHERPA is unique in combining the following features: application of multiple segmentation methods and selection of the one giving the best result for each individual object; identification of shapes of interest based on outline matching against a template library; quality scoring and ranking of resulting outlines supporting quick quality checking; extraction of a wide range of outline shape descriptors widely used in diatom studies and elsewhere; minimizing the need for, but enabling manual quality control and corrections. Although primarily developed for analyzing images of diatom valves originating from automated microscopy, SHERPA can also be useful for other object detection, segmentation and outline-based identification problems.

Erweiterung des Dokumentenservers DSpace: Internationalisierung und Implementation des URN-Systems zur permanenten Dokumentenadressierung

At first a small overview is given about the disposition of document ser- vers in the scientific publication process. Then, institutional repositories are introduced by their key features and the benefits of establishing them as a central repository in the university context. A specific solution was chosen on behalf of the requirements of the Uni- versity Library of Kassel, Germany. The software Dspace was chosen but needs to be extended by • internationalization • use of the urn:nbn scheme as persisten identifier. DSpace’s features are shortly described, followed by the process of rever- se engeneering to achieve requirements needed for the implementation of the missing functionality. Adjacent tasks implement the needed featu- res using SUN’s Standard Tag Library for internationalization and some modifications in two classes for use of the urn:nbn scheme as persistent identifier. At the end, a short view on the future of institutional repositories is taken, furthermore some local long-term objectives on DSpace are dis- cussed.

The neuroscience of cognitive enhancement : enhanced attention, working memory and visual information processing speed using 3D-MOT

Des interventions ciblant l’amélioration cognitive sont de plus en plus à l’intérêt dans nombreux domaines, y compris la neuropsychologie. Bien qu'il existe de nombreuses méthodes pour maximiser le potentiel cognitif de quelqu’un, ils sont rarement appuyé par la recherche scientifique. D’abord, ce mémoire examine brièvement l'état des interventions d'amélioration cognitives. Il décrit premièrement les faiblesses observées dans ces pratiques et par conséquent il établit un modèle standard contre lequel on pourrait et devrait évaluer les diverses techniques ciblant l'amélioration cognitive. Une étude de recherche est ensuite présenté qui considère un nouvel outil de l'amélioration cognitive, une tâche d’entrainement perceptivo-cognitive : 3-dimensional multiple object tracking (3D-MOT). Il examine les preuves actuelles pour le 3D-MOT auprès du modèle standard proposé. Les résultats de ce projet démontrent de l’augmentation dans les capacités d’attention, de mémoire de travail visuel et de vitesse de traitement d’information. Cette étude représente la première étape dans la démarche vers l’établissement du 3D-MOT comme un outil d’amélioration cognitive.

The neuroscience of cognitive enhancement : enhanced attention, working memory and visual information processing speed using 3D-MOT

Des interventions ciblant l’amélioration cognitive sont de plus en plus à l’intérêt dans nombreux domaines, y compris la neuropsychologie. Bien qu'il existe de nombreuses méthodes pour maximiser le potentiel cognitif de quelqu’un, ils sont rarement appuyé par la recherche scientifique. D’abord, ce mémoire examine brièvement l'état des interventions d'amélioration cognitives. Il décrit premièrement les faiblesses observées dans ces pratiques et par conséquent il établit un modèle standard contre lequel on pourrait et devrait évaluer les diverses techniques ciblant l'amélioration cognitive. Une étude de recherche est ensuite présenté qui considère un nouvel outil de l'amélioration cognitive, une tâche d’entrainement perceptivo-cognitive : 3-dimensional multiple object tracking (3D-MOT). Il examine les preuves actuelles pour le 3D-MOT auprès du modèle standard proposé. Les résultats de ce projet démontrent de l’augmentation dans les capacités d’attention, de mémoire de travail visuel et de vitesse de traitement d’information. Cette étude représente la première étape dans la démarche vers l’établissement du 3D-MOT comme un outil d’amélioration cognitive.

Development of a generic crop model template in the cropping system model APSIM

The Agricultural Production Systems slMulator, APSIM, is a cropping system modelling environment that simulates the dynamics of soil-plant-management interactions within a single crop or a cropping system. Adaptation of previously developed crop models has resulted in multiple crop modules in APSIM, which have low scientific transparency and code efficiency. A generic crop model template (GCROP) has been developed to capture unifying physiological principles across crops (plant types) and to provide modular and efficient code for crop modelling. It comprises a standard crop interface to the APSIM engine, a generic crop model structure, a crop process library, and well-structured crop parameter files. The process library contains the major science underpinning the crop models and incorporates generic routines based on physiological principles for growth and development processes that are common across crops. It allows APSIM to simulate different crops using the same set of computer code. The generic model structure and parameter files provide an easy way to test, modify, exchange and compare modelling approaches at process level without necessitating changes in the code. The standard interface generalises the model inputs and outputs, and utilises a standard protocol to communicate with other APSIM modules through the APSIM engine. The crop template serves as a convenient means to test new insights and compare approaches to component modelling, while maintaining a focus on predictive capability. This paper describes and discusses the scientific basis, the design, implementation and future development of the crop template in APSIM. On this basis, we argue that the combination of good software engineering with sound crop science can enhance the rate of advance in crop modelling. Crown Copyright (C) 2002 Published by Elsevier Science B.V. All rights reserved.