Implementation of placement and routing algorithms for computer aided design of printed circuit boards

The Printed Circuit Board (PCB) layout design is one of the most important and time consuming phases during equipment design process in all electronic industries. This paper is concerned with the development and implementation of a computer aided PCB design package. A set of programs which operate on a description of the circuit supplied by the user in the form of a data file and subsequently design the layout of a double-sided PCB has been developed. The algorithms used for the design of the PCB optimise the board area and the length of copper tracks used for the interconnections. The output of the package is the layout drawing of the PCB, drawn on a CALCOMP hard copy plotter and a Tektronix 4012 storage graphics display terminal. The routing density (the board area required for one component) achieved by this package is typically 0.8 sq. inch per IC. The package is implemented on a DEC 1090 system in Pascal and FORTRAN and SIGN(1) graphics package is used for display generation.

Surface Insulation Resistance Degradation and Electrochemical Migration on Printed Circuit Boards

Widespread adoption of lead-free materials and processing for printed circuit board (PCB) assembly has raised reliability concerns regarding surface insulation resistance (SIR) degradation and electrochemical migration (ECM). As PCB conductor spacings decrease, electronic products become more susceptible to these failures mechanisms, especially in the presence of surface contamination and flux residues which might remain after no-clean processing. Moreover, the probability of failure due to SIR degradation and ECM is affected by the interaction between physical factors (such as temperature, relative humidity, electric field) and chemical factors (such as solder alloy, substrate material, no-clean processing). Current industry standards for assessing SIR reliability are designed to serve as short-term qualification tests, typically lasting 72 to 168 hours, and do not provide a prediction of reliability in long-term applications. The risk of electrochemical migration with lead-free assemblies has not been adequately investigated. Furthermore, the mechanism of electrochemical migration is not completely understood. For example, the role of path formation has not been discussed in previous studies. Another issue is that there are very few studies on development of rapid assessment methodologies for characterizing materials such as solder flux with respect to their potential for promoting ECM. In this dissertation, the following research accomplishments are described: 1). Long-term temp-humidity-bias (THB) testing over 8,000 hours assessing the reliability of printed circuit boards processed with a variety of lead-free solder pastes, solder pad finishes, and substrates. 2). Identification of silver migration from Sn3.5Ag and Sn3.0Ag0.5Cu lead-free solder, which is a completely new finding compared with previous research. 3). Established the role of path formation as a step in the ECM process, and provided clarification of the sequence of individual steps in the mechanism of ECM: path formation, electrodeposition, ion transport, electrodeposition, and filament formation. 4). Developed appropriate accelerated testing conditions for assessing the no-clean processed PCBs' susceptibility to ECM: a). Conductor spacings in test structures should be reduced in order to reflect the trend of higher density electronics and the effect of path formation, independent of electric field, on the time-to-failure. b). THB testing temperatures should be modified according to the material present on the PCB, since testing at 85oC can cause the evaporation of weak organic acids (WOAs) in the flux residues, leading one to underestimate the risk of ECM. 5). Correlated temp-humidity-bias testing with ion chromatography analysis and potentiostat measurement to develop an efficient and effective assessment methodology to characterize the effect of no-clean processing on ECM.

Computational modeling techniques for reliability of electronic components on printed circuit boards

This paper describes modeling technology and its use in providing data governing the assembly and subsequent reliability of electronic chip components on printed circuit boards (PCBs). Products, such as mobile phones, camcorders, intelligent displays, etc., are changing at a tremendous rate where newer technologies are being applied to satisfy the demands for smaller products with increased functionality. At ever decreasing dimensions, and increasing number of input/output connections, the design of these components, in terms of dimensions and materials used, is playing a key role in determining the reliability of the final assembly. Multiphysics modeling techniques are being adopted to predict a range of interacting physics-based phenomena associated with the manufacturing process. For example, heat transfer, solidification, marangoni fluid flow, void movement, and thermal-stress. The modeling techniques used are based on finite volume methods that are conservative and take advantage of being able to represent the physical domain using an unstructured mesh. These techniques are also used to provide data on thermal induced fatigue which is then mapped into product lifetime predictions.

Thermogravimetric study of the decomposition of printed circuit boards from mobile phones

Thermal decomposition of printed circuits boards (PCB) is studied, using thermogravimetric analysis to compare the thermal behavior of PCB of mobile phones before and after the removal of the metallic fraction by acid washing. Several dynamic and dynamic + isothermal runs have been carried out at different heating rates (5, 10 and 20 K min−1), from room temperature to more than 1100 K. Also runs in the presence and in the absence of oxygen were performed (combustion and pyrolysis runs). Moreover, TG–MS experiments were performed (both in inert and oxidizing atmosphere) in order to better understand the thermal decomposition of these wastes and identify some compounds emitted during the controlled heating of these materials. Different reaction models are proposed, one for pyrolysis and one for combustion of the two kinds of wastes studied, which proved to simulate appropriately the experimental results at all the heating rates simultaneously.

Pollutant emissions during pyrolysis and combustion of waste printed circuit boards, before and after metal removal

The constant increase in the production of electronic devices implies the need for an appropriate management of a growing number of waste electrical and electronic equipment. Thermal treatments represent an interesting alternative to recycle this kind of waste, but particular attention has to be paid to the potential emissions of toxic by-products. In this study, the emissions from thermal degradation of printed circuit boards (with and without metals) have been studied using a laboratory scale reactor, under oxidizing and inert atmosphere at 600 and 850 °C. Apart from carbon oxides, HBr was the main decomposition product, followed by high amounts of methane, ethylene, propylene, phenol and benzene. The maximum formation of PAHs was found in pyrolysis at 850 °C, naphthalene being the most abundant. High levels of 2-, 4-, 2,4-, 2,6- and 2,4,6-bromophenols were found, especially at 600 °C. Emissions of PCDD/Fs and dioxin-like PCBs were quite low and much lower than that of PBDD/Fs, due to the higher bromine content of the samples. Combustion at 600 °C was the run with the highest PBDD/F formation: the total content of eleven 2,3,7,8-substituted congeners (tetra- through heptaBDD/Fs) was 7240 and 3250 ng WHO2005-TEQ/kg sample, corresponding to the sample with and without metals, respectively.

Kinetic Analysis and Pollutant Evolution During Thermal Degradation of Printed Circuit Boards Considering the Effect of Metals

Paper submitted to the 7th International Symposium on Feedstock Recycling of Polymeric Materials (7th ISFR 2013), New Delhi, India, 23-26 October 2013.

Thermogravimetric Study of the Decomposition of Printed Circuit Boards from Mobile Phones

Paper submitted to the 19th International Symposium on Analytical & Applied Pyrolysis, Linz, Austria, 21-25 May 2012.

Effect of Temperature, Atmosphere and Metals on the Thermal Degradation of Printed Circuit Boards

The permanent expansion of the market of electrical and electronic equipment (EEE) and the shorter innovation cycles, lead to a faster replacement of these appliances, making EEE a fast-growing source of waste (WEEE). As stated in Directive 2012/19/EU1 on waste electrical and electronic equipment, the content of hazardous components in EEE is a major concern during the waste management phase, and recycling of WEEE is not currently undertaken to a sufficient extent, resulting in a loss of valuable resources.

Emissions of Gases, Polycyclic Aromatic Hydrocarbons and Brominated Pollutants during Thermal Degradation of Waste Printed Circuit Boards

Resumen del póster presentado en Symposium on Renewable Energy and Products from Biomass and Waste, CIUDEN (Cubillos de Sil, León, Spain), 12-13 May 2015

Fast heuristic techniques for placing and wiring printed circuit boards /

Thesis--University of Illinois at Urbana-Champaign.

Optical Waveguides and Structures for Short Haul Optical Communication Channels within Printed Circuit Boards

Optical waveguides have shown promising results for use within printed circuit boards. These optical waveguides have higher bandwidth than traditional copper transmission systems and are immune to electromagnetic interference. Design parameters for these optical waveguides are needed to ensure an optimal link budget. Modeling and simulation methods are used to determine the optimal design parameters needed in designing the waveguides. As a result, optical structures necessary for incorporating optical waveguides into printed circuit boards are designed and optimized. Embedded siloxane polymer waveguides are investigated for their use in optical printed circuit boards. This material was chosen because it has low absorption, high temperature stability, and can be deposited using common processing techniques. Two sizes of waveguides are investigated, 50 $unit{mu m}$ multimode and 4 - 9 $unit{mu m}$ single mode waveguides. A beam propagation method is developed for simulating the multimode and single mode waveguide parameters. The attenuation of simulated multimode waveguides are able to match the attenuation of fabricated waveguides with a root mean square error of 0.192 dB. Using the same process as the multimode waveguides, parameters needed to ensure a low link loss are found for single mode waveguides including maximum size, minimum cladding thickness, minimum waveguide separation, and minimum bend radius. To couple light out-of-plane to a transmitter or receiver, a structure such as a vertical interconnect assembly (VIA) is required. For multimode waveguides the optimal placement of a total internal reflection mirror can be found without prior knowledge of the waveguide length. The optimal placement is found to be either 60 µm or 150 µm away from the end of the waveguide depending on which metric a designer wants to optimize the average output power, the output power variance, or the maximum possible power loss. For single mode waveguides a volume grating coupler is designed to couple light from a silicon waveguide to a polymer single mode waveguide. A focusing grating coupler is compared to a perpendicular grating coupler that is focused by a micro-molded lens. The focusing grating coupler had an optical loss of over -14 dB, while the grating coupler with a lens had an optical loss of -6.26 dB.

Maze solving automatons for self-healing of open interconnects: Modular add-on for circuit boards

We present the circuit board integration of a self-healing mechanism to repair open faults. The electric field driven mechanism physically restores fractured interconnects in electronic circuits and has the ability to solve mazes. The repair is performed by conductive particles dispersed in an insulating fluid. We demonstrate the integration of the healing module onto printed circuit boards and the ability of maze solving. We model and perform experiments on the influence of the geometry of conductive particles as well as the terminal impedances of the route on the healing efficiency. The typical heal rate is 10 mu m/s with healed route having mean resistance of 8 k Omega across a 200 micron gap and depending on the materials and concentrations used. (C) 2015 AIP Publishing LLC.