Self-consistent analysis of double-delta-doped InAlAs/InGaAs/InP HEMTs

We have carried out a theoretical study of double-delta-doped InAlAs/InGaAs/InP high electron mobility transistor (HEMT) by means of the finite differential method. The electronic states in the quantum well of the HEMT are calculated self-consistently. Instead of boundary conditions, initial conditions are used to solve the Poisson equation. The concentration of two-dimensional electron gas (2DEG) and its distribution in the HEMT have been obtained. By changing the doping density of upper and lower impurity layers we find that the 2DEG concentration confined in the channel is greatly affected by these two doping layers. But the electrons depleted by the Schottky contact are hardly affected by the lower impurity layer. It is only related to the doping density of upper impurity layer. This means that we can deal with the doping concentrations of the two impurity layers and optimize them separately. Considering the sheet concentration and the mobility of the electrons in the channel, the optimized doping densities are found to be 5 x 10(12) and 3 x 10(12) cm(-2) for the upper and lower impurity layers, respectively, in the double-delta-doped InAlAs/InGaAs/InP HEMTs.

The keys to get high transconductance of AlGaAs/InGaAs/GaAs pseudomorphic HEMTs devices

There are two key points to get high transconductance of pseudomorphic HEMTS (pHEMTs) devices. From the point view of materials, the transfer efficiency of the electrons from the delta -doped AlGaAs layer to the InGaAs channel must be high. From the point view of device processing, the gate recess depth must be carefully controlled. In the present work, AlGaAs/InGaAs/GaAs pHEMTs structures were grown by molecular beam epitaxy. Layer structures of the pHEMTs were optimized to get high transfer efficiency of the electrons. Gate recess depth was also optimized. A 0.2 mum pHEMT was fabricated on the materials with optimized layer structure using the optimized gate recess depth. The maximum transconductance of 650 mS/mm and the cut-off frequency of 81 GHz were achieved. (C) 2001 published by Elsevier Science Ltd.

Series-L/parallel-tuned comparison with shunt-C/series-tuned class-E power amplifier

An analysis of the operation of a series-L/parallel-tuned class-E amplifier and its equivalence to the classic shunt-C/series-tuned class-E amplifier are presented. The first reported closed form design equations for the series-L/parallel-tuned topology operating under ideal switching conditions are given. Furthermore, a design procedure is introduced that allows the effect that nonzero switch resistance has on amplifier performance efficiency to be accounted for. The technique developed allows optimal circuit components to be found for a given device series resistance. For a relatively high value of switching device ON series resistance of 4O, drain efficiency of around 66% for the series-L/parallel-tuned topology, and 73% for the shunt-C/series-tuned topology appear to be the theoretical limits. At lower switching device series resistance levels, the efficiency performance of each type are similar, but the series-L/parallel-tuned topology offers some advantages in terms of its potential for MMIC realisation. Theoretical analysis is confirmed by numerical simulation for a 500mW (27dBm), 10% bandwidth, 5 V series-L/parallel-tuned, then, shunt-C/series-tuned class E power amplifier, operating at 2.5 GHz, and excellent agreement between theory and simulation results is achieved. The theoretical work presented in the paper should facilitate the design of high-efficiency switched amplifiers at frequencies commensurate with the needs of modern mobile wireless applications in the microwave frequency range, where intrinsically low-output-capacitance MMIC switching devices such as pHEMTs are to be used.

Design of a LNA and a Gilbert Cell Mixer MMICs with a GaAsPHEMT technology

The design of a Gilbert Cell Mixer and a low noise amplifier (LNA), using GaAs PHEMT technology is presented. The compatibility is shown for co-integration of both block on the same chip, to form a high performance 1.9 GHz receiver front end. The designed LNA shows 9.23 dB gain and 2.01 dB noise figure (NF). The mixer is designed to operate at RF=1.9 GHz, LO=2.0 GHz and IF=100 MHz with a gain of 14.3 dB and single sideband noise figure (SSB NF) of 9.6 dB. The mixer presents a bandwith of 8 GHz.