Network node with wireless and wired interfaces: Nios II processor and uClinux to development of a NCAP embedded (IEEE 1451.1) with two interfaces, wireless (IEEE 1451.5) and wired (IEEE p1451.2)

This paper presents a NCAP embedded on DE2 kit with Nios II processor and uClinux to development of a network gateway with two interfaces, wireless (ZigBee) and wired (RS232) based on IEEE 1451. Both the communications, wireless and wired, were developed to be point-to-point and working with the same protocols, based on IEEE 1451.0-2007. The tests were made using a microcomputer, which through of browser was possible access the web page stored in the DE2 kit and send commands of control and monitoring to both TIMs (WTIM and STIM). The system describes a different form of development of the NCAP node to be applied in different environments with wired or wireless in the same node. © 2011 IEEE.

Towards a java bytecodes compiler for nios II soft-core processor

Reconfigurable computing is one of the most recent research topics in computer science. The Altera - Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs. © 2009 IEEE.

Implementação de uma plataforma HW/SW para automação industrial, utilizando hardware reconfigurável com processador NIOS II em conformidade com o padrão IEEE 1451

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Desenvolvimento de um nó de rede com diferentes interfaces de acordo com o padrão IEEE 1451 utilizando o processador nios II e o sistema operacional embarcado uclinux

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Les arts contemporànies en els llibres d'imatges per a infants II. 'Las artes contemporáneas en los libros de imágenes para niños II'.

Resumen basado en el de la autora en catalán

Acelerando algoritmos de baixo nível em visão robótica com hardware reconfigurável

A challenge that remains in the robotics field is how to make a robot to react in real time to visual stimulus. Traditional computer vision algorithms used to overcome this problem are still very expensive taking too long when using common computer processors. Very simple algorithms like image filtering or even mathematical morphology operations may take too long. Researchers have implemented image processing algorithms in high parallelism hardware devices in order to cut down the time spent in the algorithms processing, with good results. By using hardware implemented image processing techniques and a platform oriented system that uses the Nios II Processor we propose an approach that uses the hardware processing and event based programming to simplify the vision based systems while at the same time accelerating some parts of the used algorithms

IEEE 1451-based multi-interface module (I2M) for industrial processes automation

This paper describes the implementation of a multi-interface module (I2M) for automation of industrial processes, based on the IEEE1451 standard. Process automation with I2M can communicate through either wires or using wireless communication, without any hardware or software changes. We used FPGA resources to implement the I2M functions FPGA, with a NIOS II processor and ZigBee communication system (IEEE802.15), as well as RS232 serial standard. Part of the project was done in the SOPC Builder environment, which gave the designer flexibility and speed to implement the NIOS II-based microprocessor system. To test the I2M implementation, a didactic Industrial Hydraulic Module (MHI-01) was used to simulate two industrial processes to be controlled by the system proposed.

HW/SW for an intelligent transducer network based on IEEE 1451 standard

This work describes a hardware/software co-design system development, named IEEE 1451 platform, to be used in process automation. This platform intends to make easier the implementation of IEEE standards 1451.0, 1451.1, 1451.2 and 1451.5. The hardware was built using NIOS II processor resources on Alteras Cyclone II FPGA. The software was done using Java technology and C/C++ for the processors programming. This HW/SW system implements the IEEE 1451 based on a control module and supervisory software for industrial automation. © 2011 Elsevier B.V.

NCAP embedded using structured programming

This paper presents a network node embedded based on IEEE 1451 standard developed using structured programming to access the transducers in the WTIM. The NCAP was developed using Nios II processor and uClinux, a embedded operating system developed to features restricted hardware. Both hardware and software have dynamics features and they can be configured based in the application features. Based in this features, the NCAP was developed using the minimum components of hardware and software to that being implemented in remote environment like central point of data request. Many NCAP works are implemented with an object oriented structure. This is different from the surrounding implementations. In this project the NCAP was developed using structured programming. The tests of the NCAP were made using a ZigBee interface between NCAP and WTIM and the system demonstrated in areas of difficult access for long period of time due to need for low power consumption. © 2012 IEEE.

Compilação de bytecodes Java para um ambiente de arquitetura reconfigurável

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Sistema embarcado para suporte ao diagnóstico de microcalcificações em mamografias digitais

Pós-graduação em Engenharia Elétrica - FEIS

Diseño y test VHDL de un cambiador de formato para ver TV3D en un televisor convencional

La difusión de TV3D actual utiliza formatos como el Side-by-Side o Top-and-Bottom, en los que cada par de imágenes, correspondiente a las vistas de los ojos derecho e izquierdo, se encapsula con la mitad de la resolución espacial en una sola imagen. Estas imágenes se muestran de manera casi simultánea de forma que el ojo humano compone una imagen con profundidad que se asemeja a la visión binocular natural. Desde hace un par de años las principales plataformas de televisión han empezado a crear canales con contenido 3D. La televisión 3D (TV3D) se ha introducido en los hogares gracias a los televisores estereoscópicos. Estos televisores, que son compatibles con los formatos antes mencionados, extraen de cada imagen sus dos vistas, recuperan la resolución original y presentan cada vista alternativamente en la pantalla, generando al mismo tiempo una señal de sincronismo para las gafas activas, creando de esta forma la sensación tridimensional de las imágenes. En este PFC se pretende realizar el diseño VHDL de un cambiador de formato que genere en tiempo real la secuencia de imágenes correspondiente a los ojos derecho e izquierdo, con resolución completa, a partir de una secuencia codificada en formato tipo Top-and-Bottom y el banco de test para su prueba. Este circuito se implementará como un periférico del procesador NIOS II de Altera. El diseño podría utilizarse como parte de un sistema que permita la visualización de las actuales emisiones de televisión 3D en un televisor convencional. La tecnología de referencia que se utilizará serán las FPGAs, más concretamente la tarjeta Cyclone III FPGA Starter Kit (EP3C25 FPGA) de Altera, junto a una tarjeta de ampliación de Microtronix con entrada y salida HDMI para video y audio. Además se pretende crear la documentación necesaria para el desarrollo de futuros trabajos relacionados con la televisión 3D. ABSTRACT Current TV3D broadcasting uses formats as Side-by-Side or Top-and-Bottom, where every single pair of images, corresponding to left and right eyes views, are encapsulated with half spatial resolution in one single image. These images are almost simultaneously displayed so that the human eye forms an image with depth resembling naturally binocular vision. From a couple of years the major TV platforms have begun to create 3D content channels. 3D Television (3DTV) has been introduced in homes through stereoscopic televisions. These televisions, which are compatible with the above formats, each image is extracted from the two views, and recover the original resolution and displays alternately each view in screen, while generating a synchronization signal for active glasses, thereby creating the three-dimensional sensation of the images. The main objective in this PFC is to make the design of an exchanger VHDL format in real time to generate the image sequence corresponding to the right and left eyes, with full resolution from an encoded sequence type format Top-and-Bottom and test bench for testing. This circuit is implemented as a Altera NIOS II processor peripheral.The design could be used as part of a system enabling the display of current television broadcasts 3D on a conventional television. The reference technology that will be use are FPGAs, more specifically Cyclone III FPGA Starter Card Kit (EP3C25 FPGA) Altera, along with an expansion card Microtronix with HDMI input and output video and audio. It also aims to create documentation for the development of future works related to 3D TV.

Compilação para arquitetura reconfigurável

Pós-graduação em Ciência da Computação - IBILCE

Implementação Hardware/Software da estimação de movimento segundo o padrão H.264

Motion estimation is the main responsible for data reduction in digital video encoding. It is also the most computational damanding step. H.264 is the newest standard for video compression and was planned to double the compression ratio achievied by previous standards. It was developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a partnership effort known as the Joint Video Team (JVT). H.264 presents novelties that improve the motion estimation efficiency, such as the adoption of variable block-size, quarter pixel precision and multiple reference frames. This work defines an architecture for motion estimation in hardware/software, using a full search algorithm, variable block-size and mode decision. This work consider the use of reconfigurable devices, soft-processors and development tools for embedded systems such as Quartus II, SOPC Builder, Nios II and ModelSim

Arquitetura hardware/software de um núcleo NCAP segundo o padrão IEEE 1451.1: uma prova de conceito

Os sensores inteligentes são dispositivos que se diferenciam dos sensores comuns por apresentar capacidade de processamento sobre os dados monitorados. Eles tipicamente são compostos por uma fonte de alimentação, transdutores (sensores e atuadores), memória, processador e transceptor. De acordo com o padrão IEEE 1451 um sensor inteligente pode ser dividido em módulos TIM e NCAP que devem se comunicar através de uma interface padronizada chamada TII. O módulo NCAP é a parte do sensor inteligente que comporta o processador. Portanto, ele é o responsável por atribuir a característica de inteligência ao sensor. Existem várias abordagens que podem ser utilizadas para o desenvolvimento desse módulo, dentre elas se destacam aquelas que utilizam microcontroladores de baixo custo e/ou FPGA. Este trabalho aborda o desenvolvimento de uma arquitetura hardware/software para um módulo NCAP segundo o padrão IEEE 1451.1. A infra-estrutura de hardware é composta por um driver de interface RS-232, uma memória RAM de 512kB, uma interface TII, o processador embarcado NIOS II e um simulador do módulo TIM. Para integração dos componentes de hardware é utilizada ferramenta de integração automática SOPC Builder. A infra-estrutura de software é composta pelo padrão IEEE 1451.1 e pela aplicação especí ca do NCAP que simula o monitoramento de pressão e temperatura em poços de petróleo com o objetivo de detectar vazamento. O módulo proposto é embarcado em uma FPGA e para a sua prototipação é usada a placa DE2 da Altera que contém a FPGA Cyclone II EP2C35F672C6. O processador embarcado NIOS II é utilizado para dar suporte à infra-estrutura de software do NCAP que é desenvolvido na linguagem C e se baseia no padrão IEEE 1451.1. A descrição do comportamento da infra-estrutura de hardware é feita utilizando a linguagem VHDL