Adapting “8-bit” motion style to 3D computer animation for Wreck-it Ralph

Tangled (2011) demonstrated that Walt Disney Animation has successfully extended the traditional Disney animation aesthetic to the 3D medium. The very next film produced by the studio however, Wreck-it Ralph (2012), required the animators (trained in the traditional Disney style) to develop a limited style of animation inspired by the 8-bit motion of 1980s video games. This paper examines the 8-bit style motion in Wreck-it Ralph to understand if and how the principles of animation were adapted for the film.

Switching of a Sixteen Electrode Array for Wireless EIT System Using a RF-Based 8-Bit Digital Data Transmission Technique

Surface electrode switching of 16-electrode wireless EIT is studied using a Radio Frequency (RF) based digital data transmission technique operating with 8 channel encoder/decoder ICs. An electrode switching module is developed the analog multiplexers and switched with 8-bit parallel digital data transferred by transmitter/receiver module developed with radio frequency technology. 8-bit parallel digital data collected from the receiver module are converted to 16-bit digital data by using binary adder circuits and then used for switching the electrodes in opposite current injection protocol. 8-bit parallel digital data are generated using NI USB 6251 DAQ card in LabVIEW software and sent to the transmission module which transmits the digital data bits to the receiver end. Receiver module supplies the parallel digital bits to the binary adder circuits and adder circuit outputs are fed to the multiplexers of the electrode switching module for surface electrode switching. 1 mA, 50 kHz sinusoidal constant current is injected at the phantom boundary using opposite current injection protocol. The boundary potentials developed at the voltage electrodes are measured and studied to assess the wireless data transmission.

Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Effect of carrier reshaping and narrow MUX-DEMUX filtering in 0.8 bit/s/Hz WDM RZ-DPSK transmission

Effect of the carrier shape in the ultra high dense wavelength division multiplexing (WDM) return to zero differential phase shift keying (RZ-DPSK) transmission has been examined through numerical optimization of the pulse form, duty cycle and narrow multiplex/de-multiplex (MUX/DEMUX) filtering parameters. © 2007 Springer Science+Business Media, LLC.

Design of FBG-based ultra-narrow asymmetric filter for transmission with 0.8 bit/s/Hz spectral efficiency without polarisation multiplexing

We propose a novel approach to ultra-narrow optical filtering based on a specially designed slightly asymmetric filter, which can be fabricated using fibre Bragg gratings. A feasibility of 8×40 Gbit/s DWDM RZ transmission with 0.8 bit/s/Hz spectral efficiency (without polarisation multiplexing) over 1280 km of SMF/DCF link without FEC has been confirmed by numerical modelling. © 2004 Elsevier Inc. All rights reserved.

Thumb-bangers : exploring the cultural bond between video games and heavy metal

« Heavy Metal Generations » is the fourth volume in the series of papers drawn from the 2012 Music, Metal and Politics international conference (http://www.inter-disciplinary.net/publishing/product/heavy-metal-generations/).

An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-mu m CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 mu W from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP.

The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.

Rodent Scope: A User-Configurable Digital Wireless Telemetry System for Freely Behaving Animals

This paper describes the design and implementation of a wireless neural telemetry system that enables new experimental paradigms, such as neural recordings during rodent navigation in large outdoor environments. RoSco, short for Rodent Scope, is a small lightweight user-configurable module suitable for digital wireless recording from freely behaving small animals. Due to the digital transmission technology, RoSco has advantages over most other wireless modules of noise immunity and online user-configurable settings. RoSco digitally transmits entire neural waveforms for 14 of 16 channels at 20 kHz with 8-bit encoding which are streamed to the PC as standard USB audio packets. Up to 31 RoSco wireless modules can coexist in the same environment on non-overlapping independent channels. The design has spatial diversity reception via two antennas, which makes wireless communication resilient to fading and obstacles. In comparison with most existing wireless systems, this system has online user-selectable independent gain control of each channel in 8 factors from 500 to 32,000 times, two selectable ground references from a subset of channels, selectable channel grounding to disable noisy electrodes, and selectable bandwidth suitable for action potentials (300 Hz–3 kHz) and low frequency field potentials (4 Hz–3 kHz). Indoor and outdoor recordings taken from freely behaving rodents are shown to be comparable to a commercial wired system in sorting for neural populations. The module has low input referred noise, battery life of 1.5 hours and transmission losses of 0.1% up to a range of 10 m.

Security evaluation of Rakaposhi Stream Cipher

Rakaposhi is a synchronous stream cipher, which uses three main components: a non-linear feedback shift register (NLFSR), a dynamic linear feedback shift register (DLFSR) and a non-linear filtering function (NLF). NLFSR consists of 128 bits and is initialised by the secret key K. DLFSR holds 192 bits and is initialised by an initial vector (IV). NLF takes 8-bit inputs and returns a single output bit. The work identifies weaknesses and properties of the cipher. The main observation is that the initialisation procedure has the so-called sliding property. The property can be used to launch distinguishing and key recovery attacks. The distinguisher needs four observations of the related (K,IV) pairs. The key recovery algorithm allows to discover the secret key K after observing 29 pairs of (K,IV). Based on the proposed related-key attack, the number of related (K,IV) pairs is 2(128 + 192)/4 pairs. Further the cipher is studied when the registers enter short cycles. When NLFSR is set to all ones, then the cipher degenerates to a linear feedback shift register with a non-linear filter. Consequently, the initial state (and Secret Key and IV) can be recovered with complexity 263.87. If DLFSR is set to all zeros, then NLF reduces to a low non-linearity filter function. As the result, the cipher is insecure allowing the adversary to distinguish it from a random cipher after 217 observations of keystream bits. There is also the key recovery algorithm that allows to find the secret key with complexity 2 54.

Energy efficient asymmetric binary search switching technique for SAR ADC

An asymmetric binary search switching technique for a successive approximation register (SAR) ADC is presented, and trade-off between switching energy and conversion cycles is discussed. Without using any additional switches, the proposed technique consumes 46% less switching energy, for a small input swing (0.5 V-ref (P-P)), as compared to the last reported efficient switching technique in literature for an 8-bit SAR ADC. For a full input swing (2 V-ref (P-P)), the proposed technique consumes 16.5% less switching energy.