Effect of carrier reshaping and narrow MUX-DEMUX filtering in 0.8 bit/s/Hz WDM RZ-DPSK transmission

Effect of the carrier shape in the ultra high dense wavelength division multiplexing (WDM) return to zero differential phase shift keying (RZ-DPSK) transmission has been examined through numerical optimization of the pulse form, duty cycle and narrow multiplex/de-multiplex (MUX/DEMUX) filtering parameters. © 2007 Springer Science+Business Media, LLC.

Design of FBG-based ultra-narrow asymmetric filter for transmission with 0.8 bit/s/Hz spectral efficiency without polarisation multiplexing

We propose a novel approach to ultra-narrow optical filtering based on a specially designed slightly asymmetric filter, which can be fabricated using fibre Bragg gratings. A feasibility of 8×40 Gbit/s DWDM RZ transmission with 0.8 bit/s/Hz spectral efficiency (without polarisation multiplexing) over 1280 km of SMF/DCF link without FEC has been confirmed by numerical modelling. © 2004 Elsevier Inc. All rights reserved.

Thumb-bangers : exploring the cultural bond between video games and heavy metal

« Heavy Metal Generations » is the fourth volume in the series of papers drawn from the 2012 Music, Metal and Politics international conference (http://www.inter-disciplinary.net/publishing/product/heavy-metal-generations/).

Implementation of Reed-Solomon RS (255,239) Code

In this paper the construction of Reed-Solomon RS(255,239) codeword is described and the process of coding and decoding a message is simulated and verified. RS(255,239), or its shortened version RS(224,208) is used as a coding technique in Low-Power Single Carrier (LPSC) physical layer, as described in IEEE 802.11ad standard. The encoder takes 239 8-bit information symbols, adds 16 parity symbols and constructs 255-byte codeword to be transmitted through wireless communication channel. RS(255,239) codeword is defined over Galois Field GF and is used for correcting upto 8 symbol errors. RS(255,239) code construction is fully implemented and Simulink test project is constructed for testing and analyzing purposes.

Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

Chipless RFID Tag Using Multiple Microstrip Open Stub Resonators

A novel compact RFID tag employing open stubs in a microstrip transmission line is proposed. The prototype of the tag is fabricated on a substrate of dielectric constant 4.4 and loss tangent 0.0018. The tag consists of microstrip open stub resonators and cross polarized transmitting and receiving disc monopole antennas. A prototype of 8 bit data encoded tag is demonstrated in this communication. Method for enhancing the performance of the RFID tag is also proposed. Magnitude or group delay response can be used to decode the tag informations

Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.

Parallel pipelined histogram architecture via c-slow retiming

A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.

Software-based study of a non-sorting method for median calculation on a set of integer numbers

This paper presents a software-based study of a hardware-based non-sorting median calculation method on a set of integer numbers. The method divides the binary representation of each integer element in the set into bit slices in order to find the element located in the middle position. The method exhibits a linear complexity order and our analysis shows that the best performance in execution time is obtained when slices of 4-bit in size are used for 8-bit and 16-bit integers, in mostly any data set size. Results suggest that software implementation of bit slice method for median calculation outperforms sorting-based methods with increasing improvement for larger data set size. For data set sizes of N > 5, our simulations show an improvement of at least 40%.

Sistema de aquisição do ciclo pressão-volume cardíaco por métodos não-invasivos

A aquisição do ciclo pressão-volume é de grande importância para diagnóstico de cardiopatias e principalmente para o acompanhamento de intervenções terapêuticas, porém os métodos hoje utilizados são caros e agressivos ao paciente, reduzindo por estes motivos sua aplicação. Este estudo pretende obter, por métodos não-invasivos, o ciclo pressão-volume do ventrículo esquerdo de pacientes humanos. Isto consiste na aquisição dos sinais P(t) e V(t) simultaneamente e a apresentação de um gráfico P(V). Para tanto, após a revisão bibliográfica, decidiu-se utilizar a ecocardiografia com detecção automática de bordos, para obtenção do volume ventricular e a medição da onda de pressão transmitida através da artéria braquial para um manguito inflado com ar, conectado a um transdutor piezo-resistivo em ponte. A aquisição da pressão pelo método não-invasivo é comparada a dados resultantes da aquisição invasiva da pressão arterial por catéter intra-aórtico que é considerado padrãoouro. Os sinais são condicionados e digitalizados em uma placa de aquisição com conversor A/D de 8 bits e micro controlador 80c196. Os dados digitalizados são então enviados serialmente para um computador onde são gerados os gráficos. Obteve-se de cinco pacientes nove aquisições simultâneas da pressão invasiva através de catéter intra-aórtico e do protótipo desenvolvido resultando concordância segundo o método de Bland e Altman (1986) (r=0,989; d + 2s= 6,52; d - 2s =-6,07), comprovando a eficiência do método de aquisição. Obteve-se resultado satisfatório também quanto à operação sistema desenvolvido pois foram realizadas dez aquisições em cinco pacientes, registrando-se gráficos bastante similares aos apresentados na literatura disponível.

Effect of Combined Digital Imaging Parameters on Endodontic File Measurements

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Identificacao e mapeamento de areas de maior eficiencia fotossintetica para a cana-de-acucar

The objective was the study of better areas for sugar cane exploitation, using variables related to the classes and exposition of slopes, edaphic and climatic variables. Data were analysed with the aid of a Geographic Information System supported by 8 bit microcomputer, and maps of North exposition, photosynthetically the most efficient, were produced for different gradients of slope. These maps combined with traditional maps can be a very helpful tool to planners. -from English summary

Low-cost PWM speed controller for an electric mini-baja type vehicle

This paperwork presents a Pulse Width Modulation (PWM) speed controller for an electric mini-baja-type car. A battery-fed 1-kW three-phase induction motor provides the electric vehicle traction. The open-loop speed control is implemented with an equal voltage/frequency ratio, in order to maintain a constant amount of torque on all velocities. The PWM is implemented by a low-cost 8-bit microcontroller provided with optimized ROM charts for distinct speed value implementations, synchronized transition between different charts and reduced odd harmonics generation. This technique was implemented using a single passenger mini-baja vehicle, and the essays have shown that its application resulted on reduced current consumption, besides eliminating mechanical parts. Copyright © 2007 by ABCM.