Quaternary adder, subtractor and multiplier using quaternary multiplexer

Multiplexers, as in the case of binary, are very useful building blocks in the development of quaternary systems. The use of quaternary multiplexer (QMUX) in the implementation of quaternary adder, subtractor and multiplier is described in this paper. Quaternary coded decimal (QCD) adder/subtractor and quaternary excess-3 adder/subtractor realization using QMUX are also proposed

A high gain aluminium electron multiplier

A twenty stage electron multiplier using aluminium as dynode material is described. When operated in DC mode, very stable gains approaching 106 were obtained with input currents of the order of 10-12 A, even after repeated exposures to the atmospheres.

A multiplier theorem for the sublaplacian on the Heisenberg group

A multiplier theorem for the sublaplacian on the Heisenberg group is proved using Littlewood-Paley-Stein theory of g-functions.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Scan test in 18x8 bits Booth Coding-Wallace Tree multiplier

Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.

Even order harmonic Series-L/Parallel-Tuned Class-E frequency multiplier

In this brief, we propose a new Class-E frequency multiplier based on the recently introduced Series-L/Parallel-Tuned Class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.