A new low-power highly linear mixer design using differential derivative superposition

This paper presents the analysis and design of a new low power and highly linear mixer topology based on a newly reported differential derivative superposition method. Volterra series and harmonic balance are employed to investigate its linearisation mechanism and to optimise the design. A prototype mixer has been designed and is being implemented in 0.18μm CMOS technology. Simulation shows this mixer achieves 19.7dBm IIP3 with 10.5dB conversion gain, 13.2dB noise figure at 2.4GHz and only 3.8mW power consumption. This performance is competitive with already reported mixers.

Differential mixer with NMOS/PMOS stack at switching stage

This paper proposes a novel differential mixer topology. The traditional stage of switching is replaced by a stack of NMOS and PMOS transistors combined. A design is given of a 900 MHz down-conversion mixer using a 0.35 μm CMOS process. Comparison with conventional mixer shows that the topology leads to a better performance in terms of conversion gain and linearity. ©2012 IEEE.

Design of a LNA and a Gilbert Cell Mixer MMICs with a GaAs PHEMT technology

The design of a Gilbert Cell Mixer and a low noise amplifier (LNA), using GaAs PHEMT technology is presented. The compatibility is shown for co-integration of both block on the same chip, to form a high performance 1.9 GHz receiver front-end. The designed LNA shows 9.23 dB gain and 2.01 dB noise figure (NF). The mixer is designed to operate at RF=1.9 GHz, LO=2.0 GHz and IF=100 MHz with a gain of 14.3 dB and single sideband noise figure (SSB NF) of 9.6 dB. The mixer presents a bandwith of 8 GHz.

Combining ganglion cell topology and data of patients with glaucoma to determine a structure-function map

PURPOSE: To introduce techniques for deriving a map that relates visual field locations to optic nerve head (ONH) sectors and to use the techniques to derive a map relating Medmont perimetric data to data from the Heidelberg Retinal Tomograph. METHODS: Spearman correlation coefficients were calculated relating each visual field location (Medmont M700) to rim area and volume measures for 10 degrees ONH sectors (HRT III software) for 57 participants: 34 with glaucoma, 18 with suspected glaucoma, and 5 with ocular hypertension. Correlations were constrained to be anatomically plausible with a computational model of the axon growth of retinal ganglion cells (Algorithm GROW). GROW generated a map relating field locations to sectors of the ONH. The sector with the maximum statistically significant (P < 0.05) correlation coefficient within 40 degrees of the angle predicted by GROW for each location was computed. Before correlation, both functional and structural data were normalized by either normative data or the fellow eye in each participant. RESULTS: The model of axon growth produced a 24-2 map that is qualitatively similar to existing maps derived from empiric data. When GROW was used in conjunction with normative data, 31% of field locations exhibited a statistically significant relationship. This significance increased to 67% (z-test, z = 4.84; P < 0.001) when both field and rim area data were normalized with the fellow eye. CONCLUSIONS: A computational model of axon growth and normalizing data by the fellow eye can assist in constructing an anatomically plausible map connecting visual field data and sectoral ONH data.

Multi-output DC-DC converters based on diode-clamped converters configuration : topology and control strategy

This paper presents a new DC-DC Multi-Output Boost (MOB) converter which can share its total output between different series of output voltages for low and high power applications. This configuration can be utilised instead of several single output power supplies. This is a compatible topology for a diode-clamed inverter in the grid connection systems, where boosting low rectified output-voltage and series DC link capacitors is required. To verify the proposed topology, steady state and dynamic analysis of a MOB converter are examined. A simple control strategy has been proposed to demonstrate the performance of the proposed topology for a double-output boost converter. The topology and its control strategy can easily be extended to offer multiple outputs. Simulation and experimental results are presented to show the validity of the control strategy for the proposed converter.

Hybrid cascade converter topology with series connected symmetrical and asymmetrical diode-clamped H-Bridge cells

A novel H-bridge multilevel PWM converter topology based on a series connection of a high voltage (HV) diode-clamped inverter and a low voltage (LV) conventional inverter is proposed. A DC link voltage arrangement for the new hybrid and asymmetric solution is presented to have a maximum number of output voltage levels by preserving the adjacent switching vectors between voltage levels. Hence, a fifteen-level hybrid converter can be attained with a minimum number of power components. A comparative study has been carried out to present high performance of the proposed configuration to approach a very low THD of voltage and current, which leads to the possible elimination of output filter. Regarding the proposed configuration, a new cascade inverter is verified by cascading an asymmetrical diode-clamped inverter, in which nineteen levels can be synthesized in output voltage with the same number of components. To balance the DC link capacitor voltages for the maximum output voltage resolution as well as synthesise asymmetrical DC link combination, a new Multi-output Boost (MOB) converter is utilised at the DC link voltage of a seven-level H-bridge diode-clamped inverter. Simulation and hardware results based on different modulations are presented to confirm the validity of the proposed approach to achieve a high quality output voltage.

A new pulsed power supply topology based on positive buck-boost converters concept

Improving efficiency and flexibility in pulsed power supply technologies is the most substantial concern of pulsed power systems specifically with regard to plasma generation. Recently, the improvement of pulsed power supply has become of greater concern due to the extension of pulsed power applications to environmental and industrial areas. With this respect, a current source based topology is proposed in this paper as a pulsed power supply which gives the possibility of power flow control during load supplying mode. The main contribution in this configuration is utilization of low-medium voltage semiconductor switches for high voltage generation. A number of switch-diode-capacitor units are designated at the output of topology to exchange the current source energy into voltage form and generate a pulsed power with sufficient voltage magnitude and stress. Simulations carried out in Matlab/SIMULINK platform as well as experimental tests on a prototype setup have verified the capability of this topology in performing desired duties. Being efficient and flexible are the main advantages of this topology.

TOPSIG : Topology Preserving Document Signatures

Performance comparisons between File Signatures and Inverted Files for text retrieval have previously shown several significant shortcomings of file signatures relative to inverted files. The inverted file approach underpins most state-of-the-art search engine algorithms, such as Language and Probabilistic models. It has been widely accepted that traditional file signatures are inferior alternatives to inverted files. This paper describes TopSig, a new approach to the construction of file signatures. Many advances in semantic hashing and dimensionality reduction have been made in recent times, but these were not so far linked to general purpose, signature file based, search engines. This paper introduces a different signature file approach that builds upon and extends these recent advances. We are able to demonstrate significant improvements in the performance of signature file based indexing and retrieval, performance that is comparable to that of state of the art inverted file based systems, including Language models and BM25. These findings suggest that file signatures offer a viable alternative to inverted files in suitable settings and positions the file signatures model in the class of Vector Space retrieval models.

State convergence and keyspace reduction of the mixer stream cipher

This paper presents an analysis of the stream cipher Mixer, a bit-based cipher with structural components similar to the well-known Grain cipher and the LILI family of keystream generators. Mixer uses a 128-bit key and 64-bit IV to initialise a 217-bit internal state. The analysis is focused on the initialisation function of Mixer and shows that there exist multiple key-IV pairs which, after initialisation, produce the same initial state, and consequently will generate the same keystream. Furthermore, if the number of iterations of the state update function performed during initialisation is increased, then the number of distinct initial states that can be obtained decreases. It is also shown that there exist some distinct initial states which produce the same keystream, resulting in a further reduction of the effective key space

Towards persistent localization and mapping with a continuous appearance-based topology

Appearance-based localization can provide loop closure detection at vast scales regardless of accumulated metric error. However, the computation time and memory requirements of current appearance-based methods scale not only with the size of the environment but also with the operation time of the platform. Additionally, repeated visits to locations will develop multiple competing representations, which will reduce recall performance over time. These properties impose severe restrictions on long-term autonomy for mobile robots, as loop closure performance will inevitably degrade with increased operation time. In this paper we present a graphical extension to CAT-SLAM, a particle filter-based algorithm for appearance-based localization and mapping, to provide constant computation and memory requirements over time and minimal degradation of recall performance during repeated visits to locations. We demonstrate loop closure detection in a large urban environment with capped computation time and memory requirements and performance exceeding previous appearance-based methods by a factor of 2. We discuss the limitations of the algorithm with respect to environment size, appearance change over time and applications in topological planning and navigation for long-term robot operation.

Dynamic optimization of migration topology in internet-based distributed genetic algorithms

Distributed Genetic Algorithms (DGAs) designed for the Internet have to take its high communication cost into consideration. For island model GAs, the migration topology has a major impact on DGA performance. This paper describes and evaluates an adaptive migration topology optimizer that keeps the communication load low while maintaining high solution quality. Experiments on benchmark problems show that the optimized topology outperforms static or random topologies of the same degree of connectivity. The applicability of the method on real-world problems is demonstrated on a hard optimization problem in VLSI design.

A flexible solid-state pulsed power topology

Advances in solid-state switches and power electronics techniques have led to the development of compact, efficient and more reliable pulsed power systems. This paper proposes an efficient scheme that utilizes modular switch-capacitor units in obtaining high voltage levels with fast rise time (dv/dt) using low voltage solid-state switches. The proposed pulsed power supply has flexibility in terms of controlling energy and generating broad range of voltage levels. The energy flow can be controlled as the stored energy can be adjusted by a current source utilized at the first stage of the system. Desirable voltage level can be obtained by connecting adequate number of switch-capacitor units. Moreover, the proposed topology is load independent. Therefore it can easily supply wide range of applications especially the low impedance ones. The effectiveness of the proposed approach is verified by simulations

Multi-converter topology evaluation for connection of low voltage DC sources

A design for a cascaded multilevel DC-DC converter is proposed. The applications of a multilevel converter and the design issues involved in changing from a single converter to multiple converters are discussed. Implementation of the multilevel system using multiple Cuk converters is suggested and explanations of design decisions are given. The merits of the proposed design are discussed.

Part 1 MOO methods for multidisciplinary design using parallel evolutionary algorithms, game theory and hierarchical topology. (Part 1.) Theoretical aspects

Two lecture notes describe recent developments of evolutionary multi objective optimization (MO) techniques in detail and their advantages and drawbacks compared to traditional deterministic optimisers. The role of Game Strategies (GS), such as Pareto, Nash or Stackelberg games as companions or pre-conditioners of Multi objective Optimizers is presented and discussed on simple mathematical functions in Part I , as well as their implementations on simple aeronautical model optimisation problems on the computer using a friendly design framework in Part II. Real life (robust) design applications dealing with UAVs systems or Civil Aircraft and using the EAs and Game Strategies combined material of Part I & Part II are solved and discussed in Part III providing the designer new compromised solutions useful to digital aircraft design and manufacturing. Many details related to Lectures notes Part I, Part II and Part III can be found by the reader in [68].

A SiC-based matrix converter topology for inductive power transfer system

Typical inductive power transfer (IPT) systems employ two power conversion stages to generate a high-frequency primary current from low-frequency utility supply. This paper proposes a matrix-converter-based IPT system, which employs high-speed SiC devices to facilitate the generation of high-frequency current through a single power conversion stage. The proposed matrix converter topology transforms a three-phase low-frequency voltage system to a high-frequency single-phase voltage, which, in turn, powers a series compensated IPT system. A comprehensive mathematical model is developed and power losses are evaluated to investigate the efficiency of the proposed converter topology. Theoretical results are presented with simulations, which are performed in MATLAB/Simulink, in comparison to a conventional two-stage converter. Experimental evident of a prototype IPT system is also presented to demonstrate the applicability of the proposed concept.