Fractional generalization of memristor and higher order elements

Fractional calculus generalizes integer order derivatives and integrals. Memristor systems generalize the notion of electrical elements. Both concepts were shown to model important classes of phenomena. This paper goes a step further by embedding both tools in a generalization considering complex-order objects. Two complex operators leading to real-valued results are proposed. The proposed class of models generate a broad universe of elements. Several combinations of values are tested and the corresponding dynamical behavior is analyzed.

HOPF BIFURCATION FROM LINES of EQUILIBRIA WITHOUT PARAMETERS IN MEMRISTOR OSCILLATORS

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Estudo de sistemas lineares por parte com três zonas e aplicação na análise de um circuito elétrico envolvendo um memristor

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Bifurcations Leading to Nonlinear Oscillations in a 3D Piecewise Linear Memristor Oscillator

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Estabilidade de sistemas dinâmicos: Estudo do memristor

Pós-graduação em Matematica Aplicada e Computacional - FCT

Il memristor, un'innovazione nel campo dell'intelligenza artificiale: Analisi dello stato dell'arte e prospettive future

Questo elaborato concerne la revisione della letteratura scientifica relativa alla teorizzazione e realizzazione tecnologica del memristor, un nuovo componente elettronico teorizzato nel 1971 e realizzato solo nel 2008 nei laboratori della HP (Hewlett Packard, Palo Alto, California). Dopo una descrizione in termini matematici della teoria fisica alla base del dispositivo e del suo funzionamento, viene descritta la sua realizzazione tecnologica e il corrispettivo modello teorico. Succesivamente il lavoro discute la possibile analogia tra il funzionamento del memristor ed il funzionamento di neuroni e sinapsi biologiche all'interno del Sistema Nervoso Centrale. Infine, vengono descritte le architetture recentemente proposte per l'implementazione di reti neurali artificiali fondate su un sistema computazionale parallelo e realizzate mediante sistemi ibridi transistors/memristors.

A CAD framework for the characterization and use of Memristor models

In the recent years the missing fourth component, the memristor, was successfully synthesized. However, the mathematical complexity and variety of the models behind this component, in addition to the existence of convergence problems in the simulations, make the design of memristor-based applications long and difficult. In this work we present a memristor model characterization framework which supports the automated generation of subcircuit files. The proposed environment allows the designer to choose and parameterize the memristor model that best suits for a given application. The framework carries out characterizing simulations in order to study the possible non-convergence problems, solving the dependence on the simulation conditions and guaranteeing the functionality and performance of the design. Additionally, the occurrence of undesirable effects related to PVT variations is also taken into account. By performing a Monte Carlo or a corner analysis, the designer is aware of the safety margins which assure the correct device operation.

Building memristor applications: from device model to circuit design

Since the memristor was first built in 2008 at HP Labs, no end of devices and models have been presented. Also, new applications appear frequently. However, the integration of the device at the circuit level is not straightforward, because available models are still immature and/or suppose high computational loads, making their simulation long and cumbersome. This study assists circuit/systems designers in the integration of memristors in their applications, while aiding model developers in the validation of their proposals. We introduce the use of a memristor application framework to support the work of both the model developer and the circuit designer. First, the framework includes a library with the best-known memristor models, being easily extensible with upcoming models. Systematic modifications have been applied to these models to provide better convergence and significant simulations speedups. Second, a quick device simulator allows the study of the response of the models under different scenarios, helping the designer with the stimuli and operation time selection. Third, fine tuning of the device including parameters variations and threshold determination is also supported. Finally, SPICE/Spectre subcircuit generation is provided to ease the integration of the devices in application circuits. The framework provides the designer with total control overconvergence, computational load, and the evolution of system variables, overcoming usual problems in the integration of memristive devices.

Comment: Is memristor a dynamic element?

The authors present a charge/flux formulation of the equations of memristive circuits, which seemingly show that the memristor should not be considered as a dynamic circuit element. Here, is shown that this approach implicitly reduces the dynamic analysis to a certain subset of the state space in such a way that the dynamic contribution of memristors is hidden. This reduction might entail a substantial loss of information, regarding e.g. the local stability properties of the circuit. Two examples illustrate this. It is concluded that the memristor, even with its unconventional features, must be considered as a dynamic element.

Error control on spectral data of four-wave mixing based on a-SiC technology

In this paper we exploit the nonlinear property of the SiC multilayer devices to design an optical processor for error detection that enables reliable delivery of spectral data of four-wave mixing over unreliable communication channels. The SiC optical processor is realized by using double pin/pin a-SiC:H photodetector with front and back biased optical gating elements. Visible pulsed signals are transmitted together at different bit sequences. The combined optical signal is analyzed. Data show that the background acts as selector that picks one or more states by splitting portions of the input multi optical signals across the front and back photodiodes. Boolean operations such as EXOR and three bit addition are demonstrated optically, showing that when one or all of the inputs are present, the system will behave as an XOR gate representing the SUM. When two or three inputs are on, the system acts as AND gate indicating the present of the CARRY bit. Additional parity logic operations are performed using four incoming pulsed communication channels that are transmitted and checked for errors together. As a simple example of this approach, we describe an all-optical processor for error detection and then provide an experimental demonstration of this idea. (C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fractional Order Junctions

Gottfried Leibniz generalized the derivation and integration, extending the operators from integer up to real, or even complex, orders. It is presently recognized that the resulting models capture long term memory effects difficult to describe by classical tools. Leon Chua generalized the set of lumped electrical elements that provide the building blocks in mathematical models. His proposal of the memristor and of higher order elements broadened the scope of variables and relationships embedded in the development of models. This paper follows the two directions and proposes a new logical step, by generalizing the concept of junction. Classical junctions interconnect system elements using simple algebraic restrictions. Nevertheless, this simplistic approach may be misleading in the presence of unexpected dynamical phenomena and requires including additional “parasitic” elements. The novel γ-junction includes, as special cases, the standard series and parallel connections and allows a new degree of freedom when building models. The proposal motivates the search for experimental and real world manifestations of the abstract conjectures.

Memristive Computing

Memristive computing refers to the utilization of the memristor, the fourth fundamental passive circuit element, in computational tasks. The existence of the memristor was theoretically predicted in 1971 by Leon O. Chua, but experimentally validated only in 2008 by HP Labs. A memristor is essentially a nonvolatile nanoscale programmable resistor — indeed, memory resistor — whose resistance, or memristance to be precise, is changed by applying a voltage across, or current through, the device. Memristive computing is a new area of research, and many of its fundamental questions still remain open. For example, it is yet unclear which applications would benefit the most from the inherent nonlinear dynamics of memristors. In any case, these dynamics should be exploited to allow memristors to perform computation in a natural way instead of attempting to emulate existing technologies such as CMOS logic. Examples of such methods of computation presented in this thesis are memristive stateful logic operations, memristive multiplication based on the translinear principle, and the exploitation of nonlinear dynamics to construct chaotic memristive circuits. This thesis considers memristive computing at various levels of abstraction. The first part of the thesis analyses the physical properties and the current-voltage behaviour of a single device. The middle part presents memristor programming methods, and describes microcircuits for logic and analog operations. The final chapters discuss memristive computing in largescale applications. In particular, cellular neural networks, and associative memory architectures are proposed as applications that significantly benefit from memristive implementation. The work presents several new results on memristor modeling and programming, memristive logic, analog arithmetic operations on memristors, and applications of memristors. The main conclusion of this thesis is that memristive computing will be advantageous in large-scale, highly parallel mixed-mode processing architectures. This can be justified by the following two arguments. First, since processing can be performed directly within memristive memory architectures, the required circuitry, processing time, and possibly also power consumption can be reduced compared to a conventional CMOS implementation. Second, intrachip communication can be naturally implemented by a memristive crossbar structure.

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.

Nano-fabrication of complex functional structures using non- conventional lithography

In Chapter 1 I will present a brief introduction on the state of art of nanotechnologies, nanofabrication techniques and unconventional lithography as a technique to fabricate the novel electronic device as resistive switch so-called memristor is shown. In Chapter 2 a detailed description of the main fabrication and characterization techniques employed in this work is reported. Chapter 3 parallel local oxidation lithography (pLOx) describes as a main technique to obtain accurate patterning process. All the effective parameters has been studied and the optimized condition observed to highly reproducible with excellent patterned nanostructures. The effect of negative bias, calls local reduction (LR) studied. Moreover, the use of AC bias shows faster patterning process respect to DC bias. In Chapter 4 (metal/ e-SiO2/ Si nanojunction) it is shown how the electrochemical oxide nanostructures by using pLOx can be used in the fabrication of novel devices call memristor. We demonstrate a new concept, based on conventional materials, where the lifetime problem is resolved by introducing a “regeneration” step, which restores the nano-memristor to its pristine condition by applying an appropriate voltage cycle. In Chapter 5 (Graphene/ e-SiO2/ Si), Graphene as a building block material is used as an electrode to selectively oxidize the silicon substrate by pLOx set up for the fabrication of novel resistive switch device. In Chapter 6 (surface architecture) I will show another application of pLOx in biotechnology is shown. So the surface functionalization combine with nano-patterning by pLOx used to design a new surface to accurately bind biomolecules with the possibility of studying those properties and more application in nano-bio device fabrication. So, in order to obtain biochips, electronic and optical/photonics devices Nano patterning of DNA used as scaffolds to fabricate small functional nano-components.