Hierarchical Directory-Based Shared Memory Architecture

We describe the design of a directory-based shared memory architecture on a hierarchical network of hypercubes. The distributed directory scheme comprises two separate hierarchical networks for handling cache requests and transfers. Further, the scheme assumes a single address space and each processing element views the entire network as contiguous memory space. The size of individual directories stored at each node of the network remains constant throughout the network. Although the size of the directory increases with the network size, the architecture is scalable. The results of the analytical studies demonstrate superior performance characteristics of our scheme compared with those of other schemes.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Improvements in Hardware Transactional Memory for GPU Architectures

In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of computing threads, organized in SIMT fashion, requires an effective synchronization method. In contrast to CPUs, GPUs offer two memory spaces: global memory and local memory. The local memory space serves as a shared scratch-pad for a subset of the computing threads, and it is used by programmers to speed-up their applications thanks to its low latency. Prior work from the authors proposed a lightweight hardware TM (HTM) support based in the local memory, modifying the SIMT execution model and adding a conflict detection mechanism. An efficient implementation of these features is key in order to provide an effective synchronization mechanism at the local memory level. After a quick description of the main features of our HTM design for GPU local memory, in this work we gather together a number of proposals designed with the aim of improving those mechanisms with high impact on performance. Firstly, the SIMT execution model is modified to increase the parallelism of the application when transactions must be serialized in order to make forward progress. Secondly, the conflict detection mechanism is optimized depending on application characteristics, such us the read/write sets, the probability of conflict between transactions and the existence of read-only transactions. As these features can be present in hardware simultaneously, it is a task of the compiler and runtime to determine which ones are more important for a given application. This work includes a discussion on the analysis to be done in order to choose the best configuration solution.

Reflexive Incidence Matrx (RIM) Representation of Petr Nets

Although incidence matrix representation has been used to analyze the Petri net based models of a system, it has the limitation that it does not preserve reflexive properties (i.e., the presence of selfloops) of Petri nets. But in many practical applications self-loops play very important roles. This paper proposes a new representation scheme for general Petri nets. This scheme defines a matrix called "reflexive incidence matrix (RIM) c which is a combination of two matrices, a "base matrix Cb,,, and a "power matrix CP." This scheme preserves the reflexive and other properties of the Petri nets. Through a detailed analysis it is shown that the proposed scheme requires less memory space and less processing time for answering commonly encountered net queries compared to other schemes. Algorithms to generate the RIM from the given net description and to decompose RIM into input and output function matrices are also given. The proposed Petri net representation scheme is very useful to model and analyze the systems having shared resources, chemical processes, network protocols, etc., and to evaluate the performance of asynchronous concurrent systems.

SIR: A Computer Program for Semantic Information Retrieval

SIR is a computer system, programmed in the LISP language, which accepts information and answers questions expressed in a restricted form of English. This system demonstrates what can reasonably be called an ability to "understand" semantic information. SIR's semantic and deductive ability is based on the construction of an internal model, which uses word associations and property lists, for the relational information normally conveyed in conversational statements. A format-matching procedure extracts semantic content from English sentences. If an input sentence is declarative, the system adds appropriate information to the model. If an input sentence is a question, the system searches the model until it either finds the answer or determines why it cannot find the answer. In all cases SIR reports its conclusions. The system has some capacity to recognize exceptions to general rules, resolve certain semantic ambiguities, and modify its model structure in order to save computer memory space. Judging from its conversational ability, SIR, is a first step toward intelligent man-machine communication. The author proposes a next step by describing how to construct a more general system which is less complex and yet more powerful than SIR. This proposed system contains a generalized version of the SIR model, a formal logical system called SIR1, and a computer program for testing the truth of SIR1 statements with respect to the generalized model by using partial proof procedures in the predicate calculus. The thesis also describes the formal properties of SIR1 and how they relate to the logical structure of SIR.

Parallel implementation of the recurrence method for computing the power-spectral density of thin avalanche photodiodes

A simulation program has been developed to calculate the power-spectral density of thin avalanche photodiodes, which are used in optical networks. The program extends the time-domain analysis of the dead-space multiplication model to compute the autocorrelation function of the APD impulse response. However, the computation requires a large amount of memory space and is very time consuming. We describe our experiences in parallelizing the code using both MPI and OpenMP. Several array partitioning schemes and scheduling policies are implemented and tested Our results show that the OpenMP code is scalable up to 64 processors on an SGI Origin 2000 machine and has small average errors.

Parallel bandwidth characteristics calculations for thin avalanche photodiodes on a SGI Origin 2000 supercomputer

An important factor for high-speed optical communication is the availability of ultrafast and low-noise photodetectors. Among the semiconductor photodetectors that are commonly used in today’s long-haul and metro-area fiber-optic systems, avalanche photodiodes (APDs) are often preferred over p-i-n photodiodes due to their internal gain, which significantly improves the receiver sensitivity and alleviates the need for optical pre-amplification. Unfortunately, the random nature of the very process of carrier impact ionization, which generates the gain, is inherently noisy and results in fluctuations not only in the gain but also in the time response. Recently, a theory characterizing the autocorrelation function of APDs has been developed by us which incorporates the dead-space effect, an effect that is very significant in thin, high-performance APDs. The research extends the time-domain analysis of the dead-space multiplication model to compute the autocorrelation function of the APD impulse response. However, the computation requires a large amount of memory space and is very time consuming. In this research, we describe our experiences in parallelizing the code in MPI and OpenMP using CAPTools. Several array partitioning schemes and scheduling policies are implemented and tested. Our results show that the code is scalable up to 64 processors on a SGI Origin 2000 machine and has small average errors.

A hardware solution on multi-field packet classification

In this paper, a hardware solution for packet classification based on multi-fields is presented. The proposed scheme focuses on a new architecture based on the decomposition method. A hash circuit is used in order to reduce the memory space required for the Recursive Flow Classification (RFC) algorithm. The implementation results show that the proposed architecture achieves significant performance advantage that is comparable to that of some well-known algorithms. The solution is based on Altera Stratix III FPGA technology.

An Improvement of IP Address Lookup based on Rule Filter Analysis

Multi-bit trie is a popular approach performing the longest prefix matching for packet classification. However, it requires a long lookup time and inefficiently consumes memory space. This paper presents an in-depth study of different variations of multi-bit trie for IP address lookup. Our main aim is to study a method of data structure which reduces memory space. The proposed approach has been implemented using the label method in two approaches. Both methods present better results regarding lookup speed, update time and memory bit consumptions.

Traduction statistique par recherche locale

La traduction statistique vise l’automatisation de la traduction par le biais de modèles statistiques. Dans ce travail, nous relevons un des grands défis du domaine : la recherche (Brown et al., 1993). Les systèmes de traduction statistique de référence, tel Moses (Koehn et al., 2007), effectuent généralement la recherche en explorant l’espace des préfixes par programmation dynamique, une solution coûteuse sur le plan computationnel pour ce problème potentiellement NP-complet (Knight, 1999). Nous postulons qu’une approche par recherche locale (Langlais et al., 2007) peut mener à des solutions tout aussi intéressantes en un temps et un espace mémoire beaucoup moins importants (Russell et Norvig, 2010). De plus, ce type de recherche facilite l’incorporation de modèles globaux qui nécessitent des traductions complètes et permet d’effectuer des modifications sur ces dernières de manière non-continue, deux tâches ardues lors de l’exploration de l’espace des préfixes. Nos expériences nous révèlent que la recherche locale en traduction statistique est une approche viable, s’inscrivant dans l’état de l’art.

História, memória e espaços: experiências dos ex-combatentes de Parelhas-RN na defesa do litoral brasileiro durante a Segunda Guerra Mundial

The present essay has how I aim to analyse the memories of the ex-combatants of Parelhas-RN, specially of the components of the Força de Vigilância e Segurança do Litoral - FVSL, protagonists of the Brazilian participation in the scenery of the Second World war. Along this we looked to understand in which surrounding geographicalpartner these men were living before the War and what were the consequences of a brusque change of space owing to the convocation for the Armed Brazilian Strength in that historical context. The defense of the Brazilian coast during the War was not a so simple task, I have in mind the precariedade logistics of the Armed Strength, the attacks of submarines of the Axle that killed hundreds of civilians and Brazilian soldiers and the net of espionage mounted by Germany in Brazil. Leaving from the notion of collective memory and estrangement in Maurice Halbwachs, we will use the oral history like principal methodology, with the end of rescue these underground memories what also will make possible us the vision realizes that the protagonists themselves have of the event, besides the use of documents, photos, maps and any sort of fountains that make possible us to rebuild the scenery of Parelhas in the beginning of the War and the trajectory of life of his veterans

Cidade Velha e Feliz Lusitânia: cenários do Patrimônio Cultural em Belém

A Tese foi motivada pela redescoberta do bairro da Cidade Velha, na cidade de Belém, estado do Pará, redescoberta da autora em sua infância e do bairro em si enquanto espaço da memória e marco para o risorgimento do Pará. Analisa os conceitos de Patrimônio na cidade moderna, bem como a construção de um imaginário mítico que povoa a memória dos cidadãos belemenses em três etapas: da Colonização Pombalina; da Belle Èpoque e do Novo Pará. A argumentação é construída a partir de narrativas de diversos atores que interagem com o bairro: moradores antigos, moradores novos, comerciantes, técnicos do patrimônio, bem como pela leitura de imagens que ajudam a contar a história do bairro e de como ele é visto enquanto patrimônio. O método etnográfico juntamente com a semiótica foram os guias para a leitura dos materiais escritos, orais e visuais, ajudando no posicionamento da pesquisadora nos papéis de antiga moradora, arquiteta e artista plástica. Traçando um panorama sobre os conceitos de Cultura presentes na Cidade Velha, desde a visão dos residentes até a dos planejadores do projeto Feliz Lusitânia, este trabalho monta um mosaico onde aparecem as arestas entre as concepções de patrimônio dos técnicos e dos segmentos sociais.

Estudo exploratório comparativo do declínio cognitivo senil após estimulação multissensorial e cognitiva em idosos institucionalizados e não institucionalizados

O objetivo do presente trabalho foi investigar, empregando testes neuropsicológicos selecionados, a duração dos efeitos benéficos do programa de estimulação multissensorial e cognitiva realizado em idosos vivendo em instituições de longa permanência ou em comunidade. Os participantes do estudo foram idosos institucionalizados (n=20, 75,1 ± 6,8 anos de idade) e não institucionalizados (n=15, 74,1 ± 3,9 anos de idade), com 65 anos de idade ou mais, sem histórico de traumatismo crânio-encefálico, acidente vascular encefálico ou depressão primária, acuidade visual mínima 20/30 mensurada pelo Teste de Snellen e que participaram regularmente do Programa de Estimulação Multissensorial e Cognitiva. Foram realizadas reavaliações em cinco períodos (2, 4, 6, 8 e 12 meses) após a finalização da intervenção multissensorial e cognitiva. Para isso empregou-se o Mini Exame do Estado Mental (MEEM); nomeação de Boston; fluência verbal semântica (FVS) e fonológica (FVF), testes da Bateria Montreal de Avaliação da Comunicação (MAC), Teste de Narrativa “Roubo de Biscoitos” e testes neuropsicológicos selecionados da Bateria Cambridge (CANTAB) incluindo: Triagem Motora (Motor Screening – MOT); Processamento Rápido de Informação Visual (Rapid Visual Information Processing – RVP); Tempo de Reação (Reaction Time - RTI); Aprendizagem Pareada (Paired Associates Learning - PAL); Memória de Trabalho Espacial (Spatial Working Memory - SWM) e Pareamento com Atraso (Delayed matching to sample - DMS). Os resultados apontaram diferenças estatisticamente significativas entre os grupos revelando taxa de declínio cognitivo maior nos idosos institucionalizados. Esses resultados confirmam sugestão anterior de que o ambiente pobre de estímulos somato-motores e cognitivos das instituições de longa permanência aceleram o declínio cognitivo senil. Além disso, a análise das curvas ROC seguido dos cálculos de sensibilidade, especificidade e eficiência para cada teste revelou que os testes da bateria CANTAB para memória e aprendizado espacial pareado assim como para memória espacial de trabalho permitiram a distinção entre os grupos I e NI em todas janelas de reavaliação. Os resultados demonstraram que uma vez cessado o programa de estimulação, se observa em ambos os grupos declínio cognitivo progressivo, com perdas mais precoces e mais intensas nos idosos institucionalizados do que naqueles vivendo em comunidade com suas famílias. Além disso, observou-se que a duração dos efeitos benéficos sobre o desempenho nos testes neuropsicológicos de ambos os grupos é heterogêneo, e que os efeitos de proteção guardam relação estreita com a natureza das oficinas. Por conta disso os escores dos testes de linguagem declinaram mais lentamente. Os resultados reúnem evidências que permitem a recomendação de programas regulares de estimulação somatomotora e cognitiva para idosos institucionalizados com o intuito de promover a redução da taxa de progressão do declínio cognitivo senil.

Memória e Memórias: entre o eu da ficção e a ficcionalização do eu

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

João Miramar e as dobras do texto

This study about Memórias Sentimentais de João Miramar, by Oswald de Andrade, aims to explore the voices that organize the space of language in the narrative. Such space has an operative vision called polyphony, by which the signs organize themselves out of a hierarchical scale, although the chronological axis of the life of João Miramar is the guiding principle of the episodes.