Rijndael FPGA implementations utilising look-up tables

This paper presents single-chip FPGA Rijndael algorithm implementations of the Advanced Encryption Standard (AES) algorithm, Rijndael. In particular, the designs utilise look-up tables to implement the entire Rijndael Round function. A comparison is provided between these designs and similar existing implementations. Hardware implementations of encryption algorithms prove much faster than equivalent software implementations and since there is a need to perform encryption on data in real time, speed is very important. In particular, Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. In this paper, a Look-Up Table (LUT) methodology is introduced where complex and slow operations are replaced by simple LUTs. A LUT-based fully pipelined Rijndael implementation is described which has a pre-placement performance of 12 Gbits/sec, which is a factor 1.2 times faster than an alternative design in which look-up tables are utilised to implement only one of the Round function transformations, and 6 times faster than other previous single-chip implementations. Iterative Rijndael implementations based on the Look-Up-Table design approach are also discussed and prove faster than typical iterative implementations.

Partial Product Reduction based on Look-Up Tables

In this paper a new technique for partial product reduction based on the use of look-up tables for efficient processing is presented. We describe how to construct counter devices with pre-calculated data and their subsequent integration into the whole operation. The development of reduction trees organizations for this kind of devices uses the inherent integration benefits of computer memories and offers an alternative implementation to classic operation methods. Therefore, in our experiments we compare our implementation model with CMOS technology model in homogeneous terms.

Look up, look around: is there anything different about team-level OCB in China?

Ethical leadership has been widely identified as the key variable in enhancing team-level organizational citizenship behavior (team-level OCB) in western economic and business contexts. This is challenged by empirical evidence in China and findings of this study. Our study examined the relationship between ethical leadership, organizational ethical context (ethical culture and corporate ethical values) and team-level OCB. Team-level data has been collected from 57 functional teams in 57 firms operating in China. The findings suggest that although ethical leadership is positively associated with team-level OCB, ethical context positively moderates the relationship between ethical leadership and team-level OCB. The higher ethical context is found to be, the greater is the (positive) effects of ethical leadership on team-level OCB and the opposite holds true when ethical context is low. Key implications are discussed on the role of contextual ethics for team level OCB, while managerial implications include how non-Chinese firms could improve team-level OCB in the Chinese business context.

Non-linear gain - look-up table based approach for modeling a family of DC to DC converters based on transient response analysis

The purpose of this work is to propose a structure for simulating power systems using behavioral models of nonlinear DC to DC converters implemented through a look-up table of gains. This structure is specially designed for converters whose output impedance depends on the load current level, e.g. quasi-resonant converters. The proposed model is a generic one whose parameters can be obtained by direct measuring the transient response at different operating points. It also includes optional functionalities for modeling converters with current limitation and current sharing in paralleling characteristics. The pusposed structured also allows including aditional characteristics of the DC to DC converter as the efficency as a function of the input voltage and the output current or overvoltage and undervoltage protections. In addition, this proposed model is valid for overdamped and underdamped situations.

Look-up table of quadrics applied to corneal topography

Resumen de la presentación oral en el 6th EOS Topical Meeting on Visual and Physiological Optics (EMVPO 2012), Dublín, 20-22 Agosto 2012.

Look-up table of quadrics applied to corneal topography [Presentation]

Presentación oral realizada en el 6th EOS Topical Meeting on Visual and Physiological Optics (EMVPO 2012), Dublín, 20-22 Agosto 2012.

An event-based traffic flow model for traffic control at railway junctions

This paper introduces an event-based traffic model for railway systems adopting fixed-block signalling schemes. In this model, the events of trains' arrival at and departure from signalling blocks constitute the states of the traffic flow. A state transition is equivalent to the progress of the trains by one signalling block and it is realised by referring to past and present states, as well as a number of pre-calculated look-up tables of run-times in the signalling block under various signalling conditions. Simulation results are compared with those from a time-based multi-train simulator to study the improvement of processing time and accuracy.

A current error space vector based hysteresis controller with constant switching frequency and simple online boundary computation for VSI fed IM drive

This paper proposes a simple current error space vector based hysteresis controller for two-level inverter fed Induction Motor (IM) drives. This proposed hysteresis controller retains all advantages of conventional current error space vector based hysteresis controllers like fast dynamic response, simple to implement, adjacent voltage vector switching etc. The additional advantage of this proposed hysteresis controller is that it gives a phase voltage frequency spectrum exactly similar to that of a constant switching frequency space vector pulse width modulated (SVPWM) inverter. In this proposed hysteresis controller the boundary is computed online using estimated stator voltages along alpha and beta axes thus completely eliminating look up tables used for obtaining parabolic hysteresis boundary proposed in. The estimation of stator voltage is carried out using current errors along alpha and beta axes and steady state model of induction motor. The proposed scheme is simple and capable of taking inverter upto six step mode operation, if demanded by drive system. The proposed hysteresis controller based inverter fed drive scheme is simulated extensively using SIMULINK toolbox of MATLAB for steady state and transient performance. The experimental verification for steady state performance of the proposed scheme is carried out on a 3.7kW IM.

Improved design methodology for the development of electrically actuated MEMS structures

A comprehensive design flow is proposed for the design of Micro Electro Mechanical Systems that are fabricated using SOIMUMPs process. Many of the designers typically do not model the temperature dependency of electrical conductivity, thermal conductivity and convection coefficient, as it is very cumbersome to create/incorporate the same in the existing FEM simulators. Capturing these dependencies is very critical particularly for structures that are electrically actuated. Lookup tables that capture the temperature dependency of electrical conductivity, thermal conductivity and convection coefficient are created. These look up tables are taken as inputs for a commercially available FEM simulator to model the semiconductor behavior. It is demonstrated that when temperature dependency for all the above mentioned parameters is not captured, then the error in estimation of the maximum temperature (for a given structure) could be as high as 30%. Error in the estimated resistance value under the same conditions is as high as 40%. When temperature dependency of the above mentioned parameters is considered then error w.r.t the measured values is less than 5%. It is evident that error in temperature estimates leads to erroneous results from mechanical simulations as well.

High speed electro-thermal models for inverter simulations

This paper presents the application of advanced compact models of the IGBT and PIN diode to the full electrothermal system simulation of a hybrid electric vehicle converter using a look-up table of device losses. The Fourier-based solution model is used, which takes account of features such as local lifetime control and field-stop technology. Device and circuit parameters are extracted from experimental waveforms and device structural data. Matching of the switching waveforms and the resulting generation of the look-up table is presented. An example of the use of the look-up tables in simulation of inverter device temperatures is also given, for a hypothetical electric vehicle subjected to an urban driving cycle. © 2006 IEEE.

A fast detailed-chemistry modelling approach for simulating the SI-HCCI transition

An established Stochastic Reactor Model (SRM) is used to simulate the transition from Spark Ignition (SI) to Homogeneous Charge Compression Ignition (HCCI) combustion mode in a four cylinder in-line four-stroke naturally aspirated direct injection SI engine with cam profile switching. The SRM is coupled with GT-Power, a one-dimensional engine simulation tool used for modelling engine breathing during the open valve portion of the engine cycle, enabling multi-cycle simulations. The mode change is achieved by switching the cam profiles and phasing, resulting in a Negative Valve Overlap (NVO), opening the throttle, advancing the spark timing and reducing the fuel mass as well as using a pilot injection. A proven technique for tabulating the model is used to create look-up tables in both SI and HCCI modes. In HCCI mode several tables are required, including tables for the first NVO, transient valve timing NVO, transient valve timing HCCI and steady valve timing HCCI and NVO. This results in the ability to simulate the transition with detailed chemistry in very short computation times. The tables are then used to optimise the transition with the goal of reducing NO x emissions and fluctuations in IMEP. Copyright © 2010 SAE International.

A Theory of How the Brain Might Work

I wish to propose a quite speculative new version of the grandmother cell theory to explain how the brain, or parts of it, may work. In particular, I discuss how the visual system may learn to recognize 3D objects. The model would apply directly to the cortical cells involved in visual face recognition. I will also outline the relation of our theory to existing models of the cerebellum and of motor control. Specific biophysical mechanisms can be readily suggested as part of a basic type of neural circuitry that can learn to approximate multidimensional input-output mappings from sets of examples and that is expected to be replicated in different regions of the brain and across modalities. The main points of the theory are: -the brain uses modules for multivariate function approximation as basic components of several of its information processing subsystems. -these modules are realized as HyperBF networks (Poggio and Girosi, 1990a,b). -HyperBF networks can be implemented in terms of biologically plausible mechanisms and circuitry. The theory predicts a specific type of population coding that represents an extension of schemes such as look-up tables. I will conclude with some speculations about the trade-off between memory and computation and the evolution of intelligence.

Efficiency Comparison of DFT/IDFT Algorithms by Evaluating Diverse Hardware Implementations

In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inverse Fast Fourier Transformation (IFFT), and proper techniques for maximizing the FFT/IFFT execution speed, such as pipelining or parallel processing, and use of memory structures with pre-computed values (look up tables -LUT) or other dedicated hardware components (usually multipliers). Furthermore, we discuss the optimal hardware architectures that best apply to various FFT/IFFT algorithms, along with their abilities to exploit parallel processing with minimal data dependences of the FFT/IFFT calculations. An interesting approach that is also considered in this paper is the application of the integrated processing-in-memory Intelligent RAM (IRAM) chip to high speed FFT/IFFT computing. The results of the assessment study emphasize that the execution speed of the FFT/IFFT algorithms is tightly connected to the capabilities of the FFT/IFFT hardware to support the provided parallelism of the given algorithm. Therefore, we suggest that the basic Discrete Fourier Transform (DFT)/Inverse Discrete Fourier Transform (IDFT) can also provide high performances, by utilizing a specialized FFT/IFFT hardware architecture that can exploit the provided parallelism of the DFT/IDF operations. The proposed improvements include simplified multiplications over symbols given in polar coordinate system, using sinе and cosine look up tables, and an approach for performing parallel addition of N input symbols.