Partial Product Reduction based on Look-Up Tables


Autoria(s): Mora, Higinio; Mora Pascual, Jerónimo Manuel; Sanchez-Romero, Jose-Luis; Pujol, Francisco A.
Contribuinte(s)

Universidad de Alicante. Departamento de Tecnología Informática y Computación

Informática Industrial y Redes de Computadores

UniCAD: Grupo de Investigación en CAD/CAM/CAE de la Universidad de Alicante

Data(s)

04/03/2015

04/03/2015

2006

Resumo

In this paper a new technique for partial product reduction based on the use of look-up tables for efficient processing is presented. We describe how to construct counter devices with pre-calculated data and their subsequent integration into the whole operation. The development of reduction trees organizations for this kind of devices uses the inherent integration benefits of computer memories and offers an alternative implementation to classic operation methods. Therefore, in our experiments we compare our implementation model with CMOS technology model in homogeneous terms.

Identificador

19th International Conference on VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design. IEEE, 2006, 6 p.

0-7695-2502-4

1063-9667

http://hdl.handle.net/10045/45514

10.1109/VLSID.2006.130

Idioma(s)

eng

Publicador

IEEE

Relação

http://dx.doi.org/10.1109/VLSID.2006.130

Direitos

© 2006 IEEE

info:eu-repo/semantics/openAccess

Palavras-Chave #Look-Up Table #Multiplication #Specialized architecture #VLSI technology #Arquitectura y Tecnología de Computadores
Tipo

info:eu-repo/semantics/conferenceObject