An active leakage-injection scheme applied to low-voltage SRAMs

An active leakage-injection scheme (ALIS) for low-voltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a common-drain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages up to hundreds of μA at high operating temperatures. Since no additional timing is required, read-out operations are performed at no speed penalty. A simplified 256×1bit array was designed in accordance with a 0.35 CMOS process and 1.2V-supply. A range of PSPICE simulation attests the efficacy of ALIS. With an extra power consumption of 242 μW, a 200 μA-leakage @125°C, corresponding to 13.6 times the cell current, is compensated.

A 0.0016 mm(2) 0.64 nJ leakage-based CMOS temperature sensor

This paper presents a CMOS temperature sensor based on the thermal dependencies of the leakage currents targeting the 65 nm node. To compensate for the effect of process fluctuations, the proposed sensor realizes the ratio of two measures of the time it takes a capacitor to discharge through a transistor in the subthreshold regime. Furthermore, a novel charging mechanism for the capacitor is proposed to further increase the robustness against fabrication variability. The sensor, including digitization and interfacing, occupies 0.0016 mm2 and has an energy consumption of 47.7–633 pJ per sample. The resolution of the sensor is 0.28 °C, and the 3σ inaccuracy over the range 40–110 °C is 1.17 °C.

Diseño y desarrollo de un equipo de caracterización de ISFET para la medida de analitos iónicos

En este proyecto se desarrolla una unidad de medida para investigar la cuantificación de la concentración de analitos iónicos en análisis clínico mediante sensores ISFET. Para su desarrollo se precisa de un elemento que simule el comportamiento de un ISFET por lo que también se desarrolla un simulador de ISFET. Para realizar la unidad de medida se diseñan unos circuitos SMU que permiten polarizar en tensión y medir la corriente de cada terminal de un ISFET y del electrodo de referencia que actúa de puerta. El simulador se realiza con un MOSFET de la misma geometría que el ISFET y dos generadores de tensión programables. Desarrollados y validados los circuitos correspondientes, obtenemos unos excelentes resultados en el simulador que se revela de gran utilidad para la puesta en marcha de la unidad de medida, la cual ofrece unos resultados bastante buenos, si bien se aprecian ciertas corrientes de fuga que no permiten alcanzar toda la exactitud que se pretendía. Ello es debido a los circuitos impresos que deberán ser mejorados hasta conseguir la exactitud deseada. Sin embargo pueden darse por válidos los circuitos de medida diseñados.

Fabrication and characterization of silicon position sensitive particle detectors

Position sensitive particle detectors are needed in high energy physics research. This thesis describes the development of fabrication processes and characterization techniques of silicon microstrip detectors used in the work for searching elementary particles in the European center for nuclear research, CERN. The detectors give an electrical signal along the particles trajectory after a collision in the particle accelerator. The trajectories give information about the nature of the particle in the struggle to reveal the structure of the matter and the universe. Detectors made of semiconductors have a better position resolution than conventional wire chamber detectors. Silicon semiconductor is overwhelmingly used as a detector material because of its cheapness and standard usage in integrated circuit industry. After a short spread sheet analysis of the basic building block of radiation detectors, the pn junction, the operation of a silicon radiation detector is discussed in general. The microstrip detector is then introduced and the detailed structure of a double-sided ac-coupled strip detector revealed. The fabrication aspects of strip detectors are discussedstarting from the process development and general principles ending up to the description of the double-sided ac-coupled strip detector process. Recombination and generation lifetime measurements in radiation detectors are discussed shortly. The results of electrical tests, ie. measuring the leakage currents and bias resistors, are displayed. The beam test setups and the results, the signal to noise ratio and the position accuracy, are then described. It was found out in earlier research that a heavy irradiation changes the properties of radiation detectors dramatically. A scanning electron microscope method was developed to measure the electric potential and field inside irradiated detectorsto see how a high radiation fluence changes them. The method and the most important results are discussed shortly.

Effects of vacancy-type defects in silicon based particle detectors

The semiconductor particle detectors used at CERN experiments are exposed to radiation. Under radiation, the formation of lattice defects is unavoidable. The defects affect the depletion voltage and leakage current of the detectors, and hence affect on the signal-to-noise ratio of the detectors. This shortens the operational lifetime of the detectors. For this reason, the understanding of the formation and the effects of radiation induced defects is crucial for the development of radiation hard detectors. In this work, I have studied the effects of radiation induced defects-mostly vacancy related defects-with a simulation package, Silvaco. Thus, this work essentially concerns the effects of radiation induced defects, and native defects, on leakage currents in particle detectors. Impurity donor atom-vacancy complexes have been proved to cause insignificant increase of leakage current compared with the trivacancy and divacancy-oxygen centres. Native defects and divacancies have proven to cause some of the leakage current, which is relatively small compared with trivacancy and divacancy-oxygen.

Structural and electrical properties of ZnO varistors containing different spinel phases

Structural and electrical properties of ZnO varistors were investigated as a function of spinel composition. Six varistor mixtures differing only in chemical composition of spinel, were prepared by mixing separately synthesized constituent phases (DSCP method). Compositions of constituent phases in sintered samples were investigated by changes of lattice parameters of the phases, as well as by EDS analysis of the constituent phases. It was found that compositions of ZnO, intergranular and spinel phases were partially changed during sintering due to redistribution of additives, that was controlled by starting spinel composition and its stability. Electrical characterization showed significant difference in electrical properties of investigated varistors: nonlinearity coefficients ranging from 22 to 55 and leakage currents differing by the order of magnitude. Activation energies of conduction were obtained from ac impedance spectroscopy measurements. Calculated values of activation energies were in the range 0.61-1.0 eV confirming difference in defect structure of ZnO grain boundaries in varistors containing different spinel phases. (C) 2001 Elsevier B.V. Ltd and Techna S.r.l. All rights reserved.

Strain behavior of lanthanum modified BiFeO3 thin films prepared via soft chemical method

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Properties of BaBi2Ta2O9 thin films prepared by chemical solution deposition technique for dynamic random-access memory applications

We report on the properties of BaBi2Ta2O9 (BBT) thin films for dynamic random-access memory (DRAM) and integrated capacitor applications. Crystalline BBT thin films were successfully fabricated by the chemical solution deposition technique on Pt-coated Si substrates at a low annealing temperature of 650°C. The films were characterized in terms of structural, dielectric, and insulating properties. The electrical measurements were conducted on Pt/BBT/Pt capacitors. The typical measured small signal dielectric constant and dissipation factor, at 100 kHz, were 282 and 0.023, respectively, for films annealed at 700°C for 60 min. The leakage current density of the films was lower than 10-9 A/cm2 at an applied electric field of 300 kV/cm. A large storage density of 38.4 fC/μm2 was obtained at an applied electric field of 200 kV/cm. The high dielectric constant, low dielectric loss and low leakage current density suggest the suitability of BBT thin films as dielectric layer for DRAM and integrated capacitor applications.

Effect of seed addition on SnO2-based varistors for low voltage application

The effect of seed addition on the microstructure and non-ohmic properties of the SnO2 + 1%CoO + 0.05%Nb2O5 ceramic-based system was analyzed. Two classes of seeds were prepared: 99% SnO2 + 1%CuO and 99% SnO2 + 1%CoO (mol%); both classes were added to the ceramic-based system in the amount of 1%, 5%, and 10%. The two systems containing 1% of seeds resulted in a larger grain size and a lower breakdown voltage. The addition of 1% copper seeds produces a breakdown voltage (V b) of ∼ 37 V and a leakage current (fic) of 29 μA. On the other hand, the addition of 1% cobalt seeds produced a breakdown voltage of 57 V and a leakage current of 70 μA. Both systems are of great technological interest for low voltage varistor applications, by means of appropriate strategies to reduce the leakage current. Using larger amounts of seeds was not effective since the values of breakdown voltage in both cases are close to a system without seeds. To our knowledge, there are no reports in the literature regarding the use of seeds in the SnO2 system for low voltage applications. A potential barrier model which illustrates the formation of oxygen species (O′2(ads), O′ads, and O″ads) at the expense of clusters near the interface between grains is proposed. © 2012 The American Ceramic Society.

Ferroelectric and dielectric characteristics of Bi3.25La0.75Ti3O12 thin films prepared by the polymeric precursor method

The ferroelectric properties and leakage current mechanisms of preferred oriented Bi3.25La0.75 Ti3O12 (BLT) thin films deposited on La0.5Sr0.5CoO3 (LSCO) by the polymeric precursor method were investigated. Atomic force microscopy indicates that the deposited films exhibit a dense microstructure with a rather smooth surface morphology. The improved ferroelectric and leakage current characteristics can be ascribed to the plate-like grains of the BLT films. © 2006 Trans Tech Publications, Switzerland.

Surface-plasmon optical and electrochemical characterization of biofunctional surface architectures

The development and characterization of biomolecule sensor formats based on the optical technique Surface Plasmon Resonance (SPR) Spectroscopy and electrochemical methods were investigated. The study can be divided into two parts of different scope. In the first part new novel detection schemes for labeled targets were developed on the basis of the investigations in Surface-plamon Field Enhanced Spectroscopy (SPFS). The first one is SPR fluorescence imaging formats, Surface-plamon Field Enhanced Fluorescence Microscopy (SPFM). Patterned self assembled monolayers (SAMs) were prepared and used to direct the spatial distribution of biomolecules immobilized on surfaces. Here the patterned monolayers would serve as molecular templates to secure different biomolecules to known locations on a surface. The binding processed of labeled target biomolecules from solution to sensor surface were visually and kinetically recorded by the fluorescence microscope, in which fluorescence was excited by the evanescent field of propagating plasmon surface polaritons. The second format which also originates from SPFS technique, Surface-plamon Field Enhanced Fluorescence Spectrometry (SPFSm), concerns the coupling of a fluorometry to normal SPR setup. A spectrograph mounted in place of photomultiplier or microscope can provide the information of fluorescence spectrum as well as fluorescence intensity. This study also firstly demonstrated the analytical combination of surface plasmon enhanced fluorescence detection with analyte tagged by semiconducting nano- crystals (QDs). Electrochemically addressable fabrication of DNA biosensor arrays in aqueous environment was also developed. An electrochemical method was introduced for the directed in-situ assembly of various specific oligonucleotide catcher probes onto different sensing elements of a multi-electrode array in the aqueous environment of a flow cell. Surface plasmon microscopy (SPM) is utilized for the on-line recording of the various functionalization steps. Hybridization reactions between targets from solution to the different surface-bound complementary probes are monitored by surface-plasmon field-enhanced fluorescence microscopy (SPFM) using targets that are either labeled with organic dyes or with semiconducting quantum dots for color-multiplexing. This study provides a new approach for the fabrication of (small) DNA arrays and the recording and quantitative evaluation of parallel hybridization reactions. In the second part of this work, the ideas of combining the SP optical and electrochemical characterization were extended to tethered bilayer lipid membrane (tBLM) format. Tethered bilayer lipid membranes provide a versatile model platform for the study of many membrane related processes. The thiolipids were firstly self-assembled on ultraflat gold substrates. Fusion of the monolayers with small unilamellar vesicles (SUVs) formed the distal layer and the membranes thus obtained have the sealing properties comparable to those of natural membranes. The fusion could be monitored optically by SPR as an increase in reflectivity (thickness) upon formation of the outer leaflet of the bilayer. With EIS, a drop in capacitance and a steady increase in resistance could be observed leading to a tightly sealing membrane with low leakage currents. The assembly of tBLMs and the subsequent incorporation of membrane proteins were investigated with respect to their potential use as a biosensing system. In the case of valinomycin the potassium transport mediated by the ion carrier could be shown by a decrease in resistance upon increasing potassium concentration. Potential mediation of membrane pores could be shown for the ion channel forming peptide alamethicin (Alm). It was shown that at high positive dc bias (cis negative) Alm channels stay at relatively low conductance levels and show higher permeability to potassium than to tetramethylammonium. The addition of inhibitor amiloride can partially block the Alm channels and results in increase of membrane resistance. tBLMs are robust and versatile model membrane architectures that can mimic certain properties of biological membranes. tBLMs with incorporated lipopolysaccharide (LPS) and lipid A mimicking bacteria membranes were used to probe the interactions of antibodies against LPS and to investigate the binding and incorporation of the small antimicrobial peptide V4. The influence of membrane composition and charge on the behavior of V4 was also probed. This study displays the possibility of using tBLM platform to record and valuate the efficiency or potency of numerous synthesized antimicrobial peptides as potential drug candidates.

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Ratio-based temperature-sensing technique hardened against nanometer process variations

This letter presents a temperature-sensing technique on the basis of the temperature dependency of MOSFET leakage currents. To mitigate the effects of process variation, the ratio of two different leakage current measurements is calculated. Simulations show that this ratio is robust to process spread. The resulting sensor is quite small-0.0016 mm2 including an analog-to-digital conversion-and very energy efficient, consuming less than 640 pJ/conversion. After a two-point calibration, the accuracy in a range of 40°C-110°C is less than 1.5°C , which makes the technique suitable for thermal management applications.

Different approaches to grounding resistance. Calculation for thin wire structures at low frequency energization

The present paper deals with the calculation of grounding resistance of an electrode composed of thin wires, that we consider here as perfect electric conductors (PEC) e.g. with null internal resistance, when buried in a soil of uniform resistivity. The potential profile at the ground surface is also calculated when the electrode is energized with low frequency current. The classic treatment by using leakage currents, called Charge Simulated Method (CSM), is compared with that using a set of steady currents along the axis of the wires, here called the Longitudinal Currents Method (LCM), to solve the Maxwell equations. The method of moments is applied to obtain a numerical approximation of the solution by using rectangular basis functions. Both methods are applied to two types of electrodes and the results are also compared with those obtained using a thirth approach, the Average Potential Method (APM), later described in the text. From the analysis performed, we can estimate a value of the error in the determination of grounding resistance as a function of the number of segments in which the electrodes are divided.

Temperature performance of AlGaN/GaN MOS-HEMTs on Si substrates using Gd2O3 as gate dielectric

GaN based high electron mobility transistors have draw great attention due to its potential in high temperature, high power and high frequency applications [1, 2]. However, significant gate leakage current is still one of the issues which need to be solved to improve the performance and reliability of the devices [3]. Several research groups have contributed to solve this problem by using metal–oxide–semiconductor HEMTs (MOSHEMTs), with a thin dielectric layer, such as SiO2 [4], Al2O3 [5], HfO2 [6] and Gd2O3 [7] between the gate and the barrier layer on AlGaN/GaN heterostructures. Gd2O3 has shown low interfacial density of states(Dit) with GaN and a high dielectric constant and low electrical leakage currents [8], thus is considered as a promising candidate for the gate dielectrics on GaN. MOS-HEMTs using Gd2O3 grown by electron-beam heating [7] or molecular beam epitaxy (MBE) [8] on GaN or AlGan/GaN structure have been investigated, but further research is still needed in Gd2O3 based AlGaN/GaN MOSHEMTs.