Conceção de um tutorial de Iniciação ao co-projeto de Hardware/software

A crescente evolução dos dispositivos contendo circuitos integrados, em especial os FPGAs (Field Programmable Logic Arrays) e atualmente os System on a chip (SoCs) baseados em FPGAs, juntamente com a evolução das ferramentas, tem deixado um espaço entre o lançamento e a produção de materiais didáticos que auxiliem os engenheiros no Co- Projecto de hardware/software a partir dessas tecnologias. Com o intuito de auxiliar na redução desse intervalo temporal, o presente trabalho apresenta o desenvolvimento de documentos (tutoriais) direcionados a duas tecnologias recentes: a ferramenta de desenvolvimento de hardware/software VIVADO; e o SoC Zynq-7000, Z-7010, ambos desenvolvidos pela Xilinx. Os documentos produzidos são baseados num projeto básico totalmente implementado em lógica programável e do mesmo projeto implementado através do processador programável embarcado, para que seja possível avaliar o fluxo de projeto da ferramenta para um projeto totalmente implementado em hardware e o fluxo de projeto para o mesmo projeto implementado numa estrutura de harware/software.

Automatisierte Hardware-Software Partitionierung am Beispiel eines eingebetteten, echtzeitfähigen Stereobildanalysesystems in Kraftfahrzeugen

Hardware-Software Co-Design, Simulated Annealing, Real-Time Image Processing, Automated Hardware-Software Partitioning

Yingti/ruanti (hardware/software). La création d'un hall culturel hakka à Taiwan

Dans le cadre de la politique multiculturelle de protection des minorités menée par le gouvernement taïwanais, le Comité ministériel aux affaires hakka (keweihui) a planifié dix-huit « halls culturels hakkas » dans chaque comté et municipalité. L'article retrace le processus de création d'un de ces halls, dans le nord de l'île de Taiwan, au cours de la décennie 2000. L'aménagement du hall procède à l'incorporation d'artistes locaux dans une tradition nationale hakka réinventée. Il est montré comment sa genèse s'est produite à l'intersection d'une politique impulsée par « le haut » et d'un projet émanant d'acteurs locaux. L'article met en évidence comment les catégories yingti (hardware) et ruanti (software) président à sa fabrication et impliquent une opposition et une complémentarité entre « contenant » et « contenu », entre « État » et « société », qui agissent à toutes les étapes de sa mise en oeuvre.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

A compositional framework for hardware/software co-design

We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derive from a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.

Implementação Hardware/Software da estimação de movimento segundo o padrão H.264

Motion estimation is the main responsible for data reduction in digital video encoding. It is also the most computational damanding step. H.264 is the newest standard for video compression and was planned to double the compression ratio achievied by previous standards. It was developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC Moving Picture Experts Group (MPEG) as the product of a partnership effort known as the Joint Video Team (JVT). H.264 presents novelties that improve the motion estimation efficiency, such as the adoption of variable block-size, quarter pixel precision and multiple reference frames. This work defines an architecture for motion estimation in hardware/software, using a full search algorithm, variable block-size and mode decision. This work consider the use of reconfigurable devices, soft-processors and development tools for embedded systems such as Quartus II, SOPC Builder, Nios II and ModelSim

Arquitetura hardware/software de um núcleo NCAP segundo o padrão IEEE 1451.1: uma prova de conceito

Os sensores inteligentes são dispositivos que se diferenciam dos sensores comuns por apresentar capacidade de processamento sobre os dados monitorados. Eles tipicamente são compostos por uma fonte de alimentação, transdutores (sensores e atuadores), memória, processador e transceptor. De acordo com o padrão IEEE 1451 um sensor inteligente pode ser dividido em módulos TIM e NCAP que devem se comunicar através de uma interface padronizada chamada TII. O módulo NCAP é a parte do sensor inteligente que comporta o processador. Portanto, ele é o responsável por atribuir a característica de inteligência ao sensor. Existem várias abordagens que podem ser utilizadas para o desenvolvimento desse módulo, dentre elas se destacam aquelas que utilizam microcontroladores de baixo custo e/ou FPGA. Este trabalho aborda o desenvolvimento de uma arquitetura hardware/software para um módulo NCAP segundo o padrão IEEE 1451.1. A infra-estrutura de hardware é composta por um driver de interface RS-232, uma memória RAM de 512kB, uma interface TII, o processador embarcado NIOS II e um simulador do módulo TIM. Para integração dos componentes de hardware é utilizada ferramenta de integração automática SOPC Builder. A infra-estrutura de software é composta pelo padrão IEEE 1451.1 e pela aplicação especí ca do NCAP que simula o monitoramento de pressão e temperatura em poços de petróleo com o objetivo de detectar vazamento. O módulo proposto é embarcado em uma FPGA e para a sua prototipação é usada a placa DE2 da Altera que contém a FPGA Cyclone II EP2C35F672C6. O processador embarcado NIOS II é utilizado para dar suporte à infra-estrutura de software do NCAP que é desenvolvido na linguagem C e se baseia no padrão IEEE 1451.1. A descrição do comportamento da infra-estrutura de hardware é feita utilizando a linguagem VHDL

A petri net based timing model for hardware/software co-design of digital systems

We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.

Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems

The new generation of multicore processors opens new perspectives for the design of embedded systems. Multiprocessing, however, poses new challenges to the scheduling of real-time applications, in which the ever-increasing computational demands are constantly flanked by the need of meeting critical time constraints. Many research works have contributed to this field introducing new advanced scheduling algorithms. However, despite many of these works have solidly demonstrated their effectiveness, the actual support for multiprocessor real-time scheduling offered by current operating systems is still very limited. This dissertation deals with implementative aspects of real-time schedulers in modern embedded multiprocessor systems. The first contribution is represented by an open-source scheduling framework, which is capable of realizing complex multiprocessor scheduling policies, such as G-EDF, on conventional operating systems exploiting only their native scheduler from user-space. A set of experimental evaluations compare the proposed solution to other research projects that pursue the same goals by means of kernel modifications, highlighting comparable scheduling performances. The principles that underpin the operation of the framework, originally designed for symmetric multiprocessors, have been further extended first to asymmetric ones, which are subjected to major restrictions such as the lack of support for task migrations, and later to re-programmable hardware architectures (FPGAs). In the latter case, this work introduces a scheduling accelerator, which offloads most of the scheduling operations to the hardware and exhibits extremely low scheduling jitter. The realization of a portable scheduling framework presented many interesting software challenges. One of these has been represented by timekeeping. In this regard, a further contribution is represented by a novel data structure, called addressable binary heap (ABH). Such ABH, which is conceptually a pointer-based implementation of a binary heap, shows very interesting average and worst-case performances when addressing the problem of tick-less timekeeping of high-resolution timers.

Many-Core Architectures: Hardware-Software Optimization and Modeling Techniques

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore’s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.

Plataforma de Integración Hardware-Software para Testbed de Redes de Sensores Inalámbricas

El campo de las redes de sensores inalámbricas ha cobrado gran importancia en esta última década ya que se han abierto diversas líneas de investigación con el fin de poder llevar a la práctica los conceptos y definiciones que envuelven el potencial de esta tecnología, y que está llamada a ser el futuro en la adquisición de datos de cualquier entorno físico de aplicación, mediante una herramienta basada en la autogestión y desatención durante largos periodos de tiempo, capacidad de tomar muestras cuando sea necesario a través de nodos sensores que se caractericen por el ahorro de energía y que puedan ser capaces de trabajar de forma autónoma durante meses, y que el carácter inalámbrico de la red a desplegar facilite las tareas de instalación y mantenimiento. Ello requiere que las condiciones para que una red de sensores inalámbrica sea la forma más viable de monitorizar un determinado entorno se base en ciertos requisitos de diseño, como lo es la baja tasa de transferencia de datos por parte de los nodos (estos deben ser capaces de transmitir la información recolectada desde los sensores y luego permanecer dormidos hasta una nueva adquisición), hardware enfocado al bajo consumo de energía con el fin de evitar cambios en la fuente de energía (baterías) durante largos periodos de tiempo, adaptabilidad al entorno de aplicación, flexibilidad y escalabilidad de la red si la aplicación hace necesario la inclusión de nuevos nodos o la modificación de los ya existentes, sin que ello suponga mayores dificultades en su desarrollo e implementación. El Centro de Electrónica industrial de la Universidad Politécnica de Madrid se incluye dentro de este último grupo, donde se ha diseñado una completa plataforma hardware para redes de sensores inalámbricas, con el fin de investigar las potencialidades, dificultades y retos que supone el realizar un despliegue de nodos inalámbricos en cumplimiento de características primordiales como autonomía, flexibilidad y escalabilidad de la red, además de la autogestión de los dispositivos que forman parte de ella. El presente trabajo de investigación se centra en cubrir estas necesidades, por lo que su principal objetivo es la creación de una plataforma de integración hardware-software que permita explotar todas las potencialidades de la arquitectura Cookies a través de una herramienta que facilite el despliegue, control y mantenimiento de una red de sensores inalámbrica, con el fin último de contar con un sistema total para el prototipado rápido de aplicaciones, soporte de pruebas de nuevos desarrollos y la posibilidad de implementación de dicha plataforma en cualquier entorno real, siendo sólo necesario realizar pequeños ajustes desde el más alto nivel de abstracción para que el sistema sea capaz de adaptarse por sí solo. Para cumplir tales propósitos y lograr una completa integración del sistema conjunto, ha sido necesario fijar principalmente tres líneas de trabajo que se enmarcan dentro de los objetivos específicos del presente proyecto, las cuales se detallan a continuación: Bibliotecas Software modulares: Basada en la filosofía de modularidad y flexibilidad de la plataforma hardware, se hace imprescindible primeramente contar con una plataforma software para el control de todos y cada uno de los elementos que componen al nodo Cookie, a partir de bloques funcionales que permitan gestionar desde el núcleo de procesamiento principal todas las características de la plataforma. Esto permitirá asegurar el control de los recursos hardware y facilitar la utilización de la plataforma desde un nivel más alto de abstracción, sólo con la configuración de parámetros estandarizados para el funcionamiento de la misma. Perfil de aplicación Cookies: Después de contar con bloques software que permitan controlar las características de bajo nivel del nodo inalámbrico, es necesario crear una herramienta para la estandarización de la forma en la que se comunican los dispositivos a nivel de aplicación, con el fin de gestionar las características y atributos de los nodos sensores de forma remota y facilitar el entendimiento entre ellos. Para ello, es necesario fijar ciertas directivas y reglas que permitan homogeneizar la gestión de tareas asociadas a los nodos Cookies, a través del diseño de un perfil de aplicación. Testbed para redes de sensores: Como resultado de las dos líneas anteriores de trabajo, la idea es contar con un instrumento que permita realizar pruebas reales haciendo uso de la plataforma de integración HW-SW, a partir de la gestión de todas las características y potencialidades que ofrece el perfil de aplicación creado y así facilitar el desarrollo de prototipos para aplicaciones basadas en redes de sensores inalámbricas, de forma rápida y eficiente. En este sentido, la idea es contar con un banco de pruebas basado en un despliegue de nodos Cookies que pueda ser controlado desde un ordenador central a través de una interfaz de usuario, desde el cual se lleva a cabo la monitorización y actuación sobre la red inalámbrica. Con el fin de lograr todos los objetivos planteados, ha sido necesario realizar un exhaustivo estudio de la plataforma hardware descrita anteriormente con el fin de conocer la forma en la que interactúan cada uno de los elementos incluidos en los nodos, así como la arquitectura y filosofía de los mismos, para poder llevar a cabo la integración con el software y, como se verá más adelante, realizar ajustes en el hardware para poder implementar correctamente las funcionalidades diseñadas. Por otro lado, ha sido necesario analizar las características de la especificación ZigBee y, sobre todo, las propiedades que posee el módulo de comunicaciones que incluye la plataforma hardware, el ETRX2, con el fin de poder realizar una configuración y gestión adecuada de los nodos a través de la red inalámbrica, aprovechando las posibilidades y recursos que ofrece dicho módulo.

Including hardware/software co-design in the ASSERT model driven engineering process.

Abstract. The ASSERT project de?ned new software engineering methods and tools for the development of critical embedded real-time systems in the space domain. The ASSERT model-driven engineering process was one of the achievements of the project and is based on the concept of property- preserving model transformations. The key element of this process is that non-functional properties of the software system must be preserved during model transformations. Properties preservation is carried out through model transformations compliant with the Ravenscar Pro?le and provides a formal basis to the process. In this way, the so-called Ravenscar Computational Model is central to the whole ASSERT process. This paper describes the work done in the HWSWCO study, whose main objective has been to address the integration of the Hardware/Software co-design phase in the ASSERT process. In order to do that, non-functional properties of the software system must also be preserved during hardware synthesis. Keywords : Ada 2005, Ravenscar pro?le, Hardware/Software co-design, real- time systems, high-integrity systems, ORK

Hardware-software integration platform for a WSN testbed based on cookies nodes

In this work a complete hardware-software support platform for a WSN testbed focused on developing wireless sensor applications in a simple and intuitive way is presented, as an alternative of commercial-motes-based testbeds that can be found in the state of the art. The main target of this hardware-software platform is to provide the highest abstraction level on the management of WSNs but in the simplest way in order to achieve a fast profiling mechanism for reliable prototyping based on the Cookies platform as well as helping users to develop, test and validate Cookie-Based WSN applications.