Porting a Java library to different platforms

Viime aikoina matkapuhelimet ovat alkaneet tukea Javaa matkapuhelinsovellusten ohjelmointikielenä. Javan perusajatus on, että kerran käännetty sovellus voidaan suorittaa useilla laitealustoilla ilman uudelleenkääntämisen tarvetta. Jotta sovellukset voisivat toimia uudella alustalla, niiden käyttämät kirjastot tulee siirtää uudelle alustalle. Tämä diplomityö tutkii tämänkaltaiseen siirtoprojektiin liittyviä asioita. Diplomityön aikana käyttöliittymäkirjasto siirrettiin olemassa olleelta alustalta kahdelle uudelle alustalle. Toinen uusista alustoista oli vanhan alustan uusi versio, ja toinen oli kokonaan uusi alusta. Ohjelmiston siirtämistä helpottaa jos alkuperäinen ohjelmisto on suunniteltu siirrettävyyttä silmälläpitäen. Varsinaiset ohjelmaan tehtävät muutokset ovat tällöin helppoja tehdä. Hyvälaatuisen lopputuloksen saaminen vaatii kuitenkin aina että ohjelmisto myös testataan huolellisesti.

Sviluppo di modelli motore e veicolo per l'analisi di strategie di controllo in applicazioni Software e Hardware In the Loop

This work describes the development of a simulation tool which allows the simulation of the Internal Combustion Engine (ICE), the transmission and the vehicle dynamics. It is a control oriented simulation tool, designed in order to perform both off-line (Software In the Loop) and on-line (Hardware In the Loop) simulation. In the first case the simulation tool can be used in order to optimize Engine Control Unit strategies (as far as regard, for example, the fuel consumption or the performance of the engine), while in the second case it can be used in order to test the control system. In recent years the use of HIL simulations has proved to be very useful in developing and testing of control systems. Hardware In the Loop simulation is a technology where the actual vehicles, engines or other components are replaced by a real time simulation, based on a mathematical model and running in a real time processor. The processor reads ECU (Engine Control Unit) output signals which would normally feed the actuators and, by using mathematical models, provides the signals which would be produced by the actual sensors. The simulation tool, fully designed within Simulink, includes the possibility to simulate the only engine, the transmission and vehicle dynamics and the engine along with the vehicle and transmission dynamics, allowing in this case to evaluate the performance and the operating conditions of the Internal Combustion Engine, once it is installed on a given vehicle. Furthermore the simulation tool includes different level of complexity, since it is possible to use, for example, either a zero-dimensional or a one-dimensional model of the intake system (in this case only for off-line application, because of the higher computational effort). Given these preliminary remarks, an important goal of this work is the development of a simulation environment that can be easily adapted to different engine types (single- or multi-cylinder, four-stroke or two-stroke, diesel or gasoline) and transmission architecture without reprogramming. Also, the same simulation tool can be rapidly configured both for off-line and real-time application. The Matlab-Simulink environment has been adopted to achieve such objectives, since its graphical programming interface allows building flexible and reconfigurable models, and real-time simulation is possible with standard, off-the-shelf software and hardware platforms (such as dSPACE systems).

Hardware-based and Software-based Security in Digital Rights Management Solutions

The main requirements to DRM platforms implementing effective user experience and strong security measures to prevent unauthorized use of content are discussed. Comparison of hardware-based and software- based platforms is made showing the general inherent advantages of hardware DRM solutions. Analysis and evaluation of the main flaws of hardware platforms are conducted, pointing out the possibilities to overcome them. The overview of the existing concepts for practical realization of hardware DRM protection reveals their advantages and disadvantages and the increasing demand for creation of multi-core architecture, which could assure an effective DRM protection without decreasing the user’s freedom and importing risks for end system security.

Digital surveillance based on video CODEC System-on-a-Chip (SoC) platforms

Today, most conventional surveillance networks are based on analog system, which has a lot of constraints like manpower and high-bandwidth requirements. It becomes the barrier for today's surveillance network development. This dissertation describes a digital surveillance network architecture based on the H.264 coding/decoding (CODEC) System-on-a-Chip (SoC) platform. The proposed digital surveillance network architecture includes three major layers: software layer, hardware layer, and the network layer. The following outlines the contributions to the proposed digital surveillance network architecture. (1) We implement an object recognition system and an object categorization system on the software layer by applying several Digital Image Processing (DIP) algorithms. (2) For better compression ratio and higher video quality transfer, we implement two new modules on the hardware layer of the H.264 CODEC core, i.e., the background elimination module and the Directional Discrete Cosine Transform (DDCT) module. (3) Furthermore, we introduce a Digital Signal Processor (DSP) sub-system on the main bus of H.264 SoC platforms as the major hardware support system for our software architecture. Thus we combine the software and hardware platforms to be an intelligent surveillance node. Lab results show that the proposed surveillance node can dramatically save the network resources like bandwidth and storage capacity.

Balancing Energy and Performance in Dense Linear System Solvers for Hybrid ARM+GPU platforms

The high performance computing community has traditionally focused uniquely on the reduction of execution time, though in the last years, the optimization of energy consumption has become a main issue. A reduction of energy usage without a degradation of performance requires the adoption of energy-efficient hardware platforms accompanied by the development of energy-aware algorithms and computational kernels. The solution of linear systems is a key operation for many scientific and engineering problems. Its relevance has motivated an important amount of work, and consequently, it is possible to find high performance solvers for a wide variety of hardware platforms. In this work, we aim to develop a high performance and energy-efficient linear system solver. In particular, we develop two solvers for a low-power CPU-GPU platform, the NVIDIA Jetson TK1. These solvers implement the Gauss-Huard algorithm yielding an efficient usage of the target hardware as well as an efficient memory access. The experimental evaluation shows that the novel proposal reports important savings in both time and energy-consumption when compared with the state-of-the-art solvers of the platform.

Urubu: energy scavenging in wireless sensor networks

For the past years wireless sensor networks (WSNs) have been coined as one of the most promising technologies for supporting a wide range of applications. However, outside the research community, few are the people who know what they are and what they can offer. Even fewer are the ones that have seen these networks used in real world applications. The main obstacle for the proliferation of these networks is energy, or the lack of it. Even though renewable energy sources are always present in the networks environment, designing devices that can efficiently scavenge that energy in order to sustain the operation of these networks is still an open challenge. Energy scavenging, along with energy efficiency and energy conservation, are the current available means to sustain the operation of these networks, and can all be framed within the broader concept of “Energetic Sustainability”. A comprehensive study of the several issues related to the energetic sustainability of WSNs is presented in this thesis, with a special focus in today’s applicable energy harvesting techniques and devices, and in the energy consumption of commercially available WSN hardware platforms. This work allows the understanding of the different energy concepts involving WSNs and the evaluation of the presented energy harvesting techniques for sustaining wireless sensor nodes. This survey is supported by a novel experimental analysis of the energy consumption of the most widespread commercially available WSN hardware platforms.

Ferramenta de apoio ao projeto, configuração e gestão de instalações domóticas

Esta dissertação apresenta o trabalho realizado no âmbito da unidade curricular de Tese / Dissertação (TEDI) do Mestrado em Engenharia Eletrotécnica e de Computadores – Especialização em Automação e Sistemas em parceria com a empresa Live Simply, uma empresa de domótica que decidiu apostar na inovação e no desenvolvimento de serviços e produtos de valor acrescentado para consolidar a sua posição no mercado. Neste contexto, foram identificadas como mais-valias para a Live Simply a conceção, por um lado, de uma ferramenta de apoio técnico de integração e simplificação das fases de projeto, configuração e gestão de instalações domóticas e, por outro lado, de uma interface com a instalação para o cliente consultar e alterar, em tempo real, o estado dos atuadores. Depois de analisadas as tecnologias disponíveis, selecionaram-se as soluções a adotar (linguagens de programação, servidores de base de dados e ambientes de desenvolvimento), definiu-se a arquitetura do sistema, detalhando-se os módulos de projeto, configuração e gestão de instalações, a estrutura da base de dados assim como o hardware de controlo da instalação. De seguida, procedeu-se ao desenvolvimento dos módulos de software e à configuração e programação do módulo de hardware. Por último, procedeu-se a um conjunto exaustivo de testes aos diferentes módulos que demonstraram o correto funcionamento da ferramenta e a adequação das tecnologias empregues. A ferramenta de apoio técnico realizada integra as fases do projeto, configuração e gestão de instalações domóticas, permitindo melhorar o desempenho dos técnicos e a resposta aos clientes. A interface oferecida ao dono da instalação é uma interface Web de aspeto amigável e fácil utilização que permite consultar e modificar em tempo real o estado da instalação.

Multifunctional controller architecture for sold-state marx modulator based on FPGA

This paper proposes a multifunctional architecture to implement field-programmable gate array (FPGA) controllers for power converters and presents a prototype for a pulsed power generator based on a solid-state Marx topology. The massively parallel nature of reconfigurable hardware platforms provides very high processing power and fast response times allowing the implementation of many subsystems in the same device. The prototype includes the controller, a failure detection system, an interface with a safety/emergency subsystem, a graphical user interface, and a virtual oscilloscope to visualize the generated pulse waveforms, using a single FPGA. The proposed architecture employs a modular design that can be easily adapted to other power converter topologies.

Reconfigurable IEEE1451-FPGA based weblab infrastructure

Weblabs are spreading their influence in Science and Engineering (S&E) courses providing a way to remotely conduct real experiments. Typically, they are implemented by different architectures and infrastructures supported by Instruments and Modules (I&Ms) able to be remotely controlled and observed. Besides the inexistence of a standard solution for implementing weblabs, their reconfiguration is limited to a setup procedure that enables interconnecting a set of preselected I&Ms into an Experiment Under Test (EUT). Moreover, those I&Ms are not able to be replicated or shared by different weblab infrastructures, since they are usually based on hardware platforms. Thus, to overcome these limitations, this paper proposes a standard solution that uses I&Ms embedded into Field-Programmable Gate Array (FPGAs) devices. It is presented an architecture based on the IEEE1451.0 Std. supported by a FPGA-based weblab infrastructure able to be remotely reconfigured with I&Ms, described through standard Hardware Description Language (HDL) files, using a Reconfiguration Tool (RecTool).

How realistic is the mixed-criticality real-time system model?

23rd International Conference on Real-Time Networks and Systems (RTNS 2015). 4 to 6, Nov, 2015, Main Track. Lille, France. Best Paper Award Nominee

Service-oriented architecture for device lifecycle support in industrial automation

Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores Especialidade: Robótica e Manufactura Integrada

Estudi GPGPU dedicat al processament de neuroimatges

La tecnologia GPGPU permet paral∙lelitzar càlculs executant operacions aritmètiques en els múltiples processadors de que disposen els xips gràfics. S'ha fet servir l'entorn de desenvolupament CUDA de la companyia NVIDIA, que actualment és la solució GPGPU més avançada del mercat. L'algorisme de neuroimatge implementat pertany a un estudi VBM desenvolupat amb l'eina SPM. Es tracta concretament del procés de segmentació d'imatges de ressonància magnètica cerebrals, en els diferents teixits dels quals es composa el cervell: matèria blanca, matèria grisa i líquid cefaloraquidi. S'han implementat models en els llenguatges Matlab, C i CUDA, i s'ha fet un estudi comparatiu per plataformes hardware diferents.

Virtual Radio Engine

Software Defined Radio (SDR) hardware platforms use parallel architectures. Current concepts of developing applications (such as WLAN) for these platforms are complex, because developers describe an application with hardware-specifics that are relevant to parallelism such as mapping and scheduling. To reduce this complexity, we have developed a new programming approach for SDR applications, called Virtual Radio Engine (VRE). VRE defines a language for describing applications, and a tool chain that consists of a compiler kernel and other tools (such as a code generator) to generate executables. The thesis presents this concept, as well as describes the language and the compiler kernel that have been developed by the author. The language is hardware-independent, i.e., developers describe tasks and dependencies between them. The compiler kernel performs automatic parallelization, i.e., it is capable of transforming a hardware-independent program into a hardware-specific program by solving hardware-specifics, in particular mapping, scheduling and synchronizations. Thus, VRE simplifies programming tasks as developers do not solve hardware-specifics manually.

FAMOUS, faster: using parallel computing techniques to accelerate the FAMOUS/HadCM3 climate model with a focus on the radiative transfer algorithm

We have optimised the atmospheric radiation algorithm of the FAMOUS climate model on several hardware platforms. The optimisation involved translating the Fortran code to C and restructuring the algorithm around the computation of a single air column. Instead of the existing MPI-based domain decomposition, we used a task queue and a thread pool to schedule the computation of individual columns on the available processors. Finally, four air columns are packed together in a single data structure and computed simultaneously using Single Instruction Multiple Data operations. The modified algorithm runs more than 50 times faster on the CELL’s Synergistic Processing Elements than on its main PowerPC processing element. On Intel-compatible processors, the new radiation code runs 4 times faster. On the tested graphics processor, using OpenCL, we find a speed-up of more than 2.5 times as compared to the original code on the main CPU. Because the radiation code takes more than 60% of the total CPU time, FAMOUS executes more than twice as fast. Our version of the algorithm returns bit-wise identical results, which demonstrates the robustness of our approach. We estimate that this project required around two and a half man-years of work.