Taper-free and vertically oriented Ge nanowires on Ge/Si substrates grown by a two-temperature process

Taper-free and vertically oriented Ge nanowires were grown on Si (111) substrates by chemical vapor deposition with Au nanoparticle catalysts. To achieve vertical nanowire growth on the highly lattice mismatched Si substrate, a thin Ge buffer layer was first deposited, and to achieve taper-free nanowire growth, a two-temperature process was employed. The two-temperature process consisted of a brief initial base growth step at high temperature followed by prolonged growth at lower temperature. Taper-free and defect-free Ge nanowires grew successfully even at 270 °C, which is 90 °C lower than the bulk eutectic temperature. The yield of vertical and taper-free nanowires is over 90%, comparable to that of vertical but tapered nanowires grown by the conventional one-temperature process. This method is of practical importance and can be reliably used to develop novel nanowire-based devices on relatively cheap Si substrates. Additionally, we observed that the activation energy of Ge nanowire growth by the two-temperature process is dependent on Au nanoparticle size. The low activation energy (∼5 kcal/mol) for 30 and 50 nm diameter Au nanoparticles suggests that the decomposition of gaseous species on the catalytic Au surface is a rate-limiting step. A higher activation energy (∼14 kcal/mol) was determined for 100 nm diameter Au nanoparticles which suggests that larger Au nanoparticles are partially solidified and that growth kinetics become the rate-limiting step. © 2011 American Chemical Society.

Vertically standing Ge nanowires on GaAs(110) substrates.

The growth of epitaxial Ge nanowires is investigated on (100), (111) B and (110) GaAs substrates in the growth temperature range from 300 to 380 °C. Unlike epitaxial Ge nanowires on Ge or Si substrates, Ge nanowires on GaAs substrates grow predominantly along the [Formula: see text] direction. Using this unique property, vertical [Formula: see text] Ge nanowires epitaxially grown on GaAs(110) surface are realized. In addition, these Ge nanowires exhibit minimal tapering and uniform diameters, regardless of growth temperatures, which is an advantageous property for device applications. Ge nanowires growing along the [Formula: see text] directions are particularly attractive candidates for forming nanobridge devices on conventional (100) surfaces.

Disorder induced interface states and their influence on the AI/Ge nanowires Schottky devices

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

AuxAg1-x alloy seeds: A way to control growth, morphology and defect formation in Ge nanowires

Germanium (Ge) nanowires are of current research interest for high speed nanoelectronic devices due to the lower band gap and high carrier mobility compatible with high K-dielectrics and larger excitonic Bohr radius ensuing a more pronounced quantum confinement effect [1-6]. A general way for the growth of Ge nanowires is to use liquid or a solid growth promoters in a bottom-up approach which allow control of the aspect ratio, diameter, and structure of 1D crystals via external parameters, such as precursor feedstock, temperature, operating pressure, precursor flow rate etc [3, 7-11]. The Solid-phase seeding is preferred for more control processing of the nanomaterials and potential suppression of the unintentional incorporation of high dopant concentrations in semiconductor nanowires and unrequired compositional tailing of the seed-nanowire interface [2, 5, 9, 12]. There are therefore distinct features of the solid phase seeding mechanism that potentially offer opportunities for the controlled processing of nanomaterials with new physical properties. A superior control over the growth kinetics of nanowires could be achieved by controlling the inherent growth constraints instead of external parameters which always account for instrumental inaccuracy. The high dopant concentrations in semiconductor nanowires can result from unintentional incorporation of atoms from the metal seed material, as described for the Al catalyzed VLS growth of Si nanowires [13] which can in turn be depressed by solid-phase seeding. In addition, the creation of very sharp interfaces between group IV semiconductor segments has been achieved by solid seeds [14], whereas the traditionally used liquid Au particles often leads to compositional tailing of the interface [15] . Korgel et al. also described the superior size retention of metal seeds in a SFSS nanowire growth process, when compared to a SFLS process using Au colloids [12]. Here in this work we have used silver and alloy seed particle with different compositions to manipulate the growth of nanowires in sub-eutectic regime. The solid seeding approach also gives an opportunity to influence the crystallinity of the nanowires independent of the substrate. Taking advantage of the readily formation of stacking faults in metal nanoparticles, lamellar twins in nanowires could be formed.

Fingerprints of a size-dependent crossover in the dimensionality of electronic conduction in Au-seeded Ge nanowires

We studied the electrical transport properties of Au-seeded germanium nanowires with radii ranging from 11 to 80 nm at ambient conditions. We found a non-trivial dependence of the electrical conductivity, mobility and carrier density on the radius size. In particular, two regimes were identified for large (lightly doped) and small (stronger doped) nanowires in which the charge-carrier drift is dominated by electron-phonon and ionized-impurity scattering, respectively. This goes in hand with the finding that the electrostatic properties for radii below ca. 37 nm have quasi one-dimensional character as reflected by the extracted screening lengths.

Beneficial defects : exploiting the intrinsic polishing-induced wafer roughness for the catalyst-free growth of Ge in-plane nanowires

We outline a metal-free fabrication route of in-plane Ge nanowires on Ge(001) substrates. By positively exploiting the polishing-induced defects of standard-quality commercial Ge(001) wafers, micrometer-length wires are grown by physical vapor deposition in ultra-high-vacuum environment. The shape of the wires can be tailored by the epitaxial strain induced by subsequent Si deposition, determining a progressive transformation of the wires in SiGe faceted quantum dots. This shape transition is described by finite element simulations of continuous elasticity and gives hints on the equilibrium shape of nanocrystals in the presence of tensile epitaxial strain.

Growth and characterization of germanium nanowires by electron beam evaporation

Germanium nanowires were grown on Au coated Si substrates at 380 degrees C in a high vacuum (5 x 10(-5) Torr) by e-beam evaporation of Germanium (Ge). The morphology observation by a field emission scanning electron microscope (FESEM) shows that the grown nanowires are randomly oriented with an average length and diameter of 600 nm and 120 nm respectively for a deposition time of 60 min. The nanowire growth ratewas measured to be similar to 10 nm/min. Transmission electron microscope (TEM) studies revealed that the Ge nanowires were single crystalline in nature and further energy dispersive X-ray analysis(EDAX) has shown that the tip of the grown nanowires was capped with Au nanoparticles, this shows that the growth of the Ge nanowires occurs by the vapour liquid solid (VLS) mechanism. HRTEM studies on the grown Ge nanowire show that they are single crystalline in nature and the growth direction was identified to be along [110]. (C) 2010 Elsevier B.V. All rights reserved.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates. Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seed nanowire growth via a vapor-liquid-solid growth mechanism. Rapid oxidation of Si during Au nanoparticle application inhibits the growth of vertically oriented Ge nanowires directly on Si. The present method employs thin Ge buffer layers grown at low temperature less than 600 degrees C to circumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughness of approximately 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield is comparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowires could be successfully grown on these vertically oriented Ge nanowires by a secondary seeding technique. Since the buffer layers are grown under moderate conditions without any high temperature processing steps, this method has a wide process window highly suitable for Si-based microelectronics.

Synthesis & characterisation of group IV semiconducting nanowires

Semiconductor nanowires, particularly group 14 semiconductor nanowires, have been the subject of intensive research in the recent past. They have been demonstrated to provide an effective, versatile route towards the continued miniaturisation and improvement of microelectronics. This thesis aims to highlight some novel ways of fabricating and controlling various aspects of the growth of Si and Ge nanowires. Chapter 1 highlights the primary technique used for the growth of nanowires in this study, namely, supercritical fluid (SCF) growth reactions. The advantages (and disadvantages) of this technique for the growth of Si and Ge nanowires are highlighted, citing numerous examples from the past ten years. The many variables involved in this technique are discussed along with the resultant characteristics of nanowires produced (diameter, doping, orientation etc.). Chapter 2 outlines the experimental methodologies used in this thesis. The analytical techniques used for the structural characterisation of nanowires produced are also described as well as the techniques used for the chemical analysis of various surface terminations. Chapter 3 describes the controlled self-seeded growth of highly crystalline Ge nanowires, in the absence of conventional metal seed catalysts, using a variety of oligosilylgermane precursors and mixtures of germane and silane compounds. A model is presented which describes the main stages of self-seeded Ge nanowire growth (nucleation, coalescence and Ostwald ripening) from the oligosilylgermane precursors and in conjunction with TEM analysis, a mechanism of growth is proposed. Chapter 4 introduces the metal assisted etching (MAE) of Si substrates to produce Si nanowires. A single step metal-assisted etch (MAE) process, utilising metal ion-containing HF solutions in the absence of an external oxidant, was developed to generate heterostructured Si nanowires with controllable porous (isotropically etched) and non-porous (anisotropically etched) segments. In Chapter 5 the bottom-up growth of Ge nanowires, similar to that described in Chapter 3, and the top down etching of Si, described in Chapter 4, are combined. The introduction of a MAE processing step in order to “sink” the Ag seeds into the growth substrate, prior to nanowire growth, is shown to dramatically decrease the mean nanowire diameters and to narrow the diameter distributions. Finally, in Chapter 6, the biotin – streptavidin interaction was explored for the purposes of developing a novel Si junctionless nanowire transistor (JNT) sensor.

Fabrication and characterisation of semiconductor nanowires and metal interconnects

One-dimensional semiconductor nanowires are considered to be promising materials for future nanoelectronic applications. However, before these nanowires can be integrated into such applications, a thorough understanding of their growth behaviour is necessary. In particular, methods that allow the control over nanowire growth are deemed especially important as it is these methods that will enable the control of nanowire dimensions such as length and diameter (high aspect ratios). The production of nanowires with high-aspect ratios is vital in order to take advantage of the unique properties experienced at the nanoscale, thus allowing us to maximise their use in devices. Additionally, the development of low-resistivity interconnects is desirable in order to connect such nanowires in multi-nanowire components. Consequently, this thesis aims to discuss the synthesis and characterisation of germanium (Ge) nanowires and platinum (Pt) interconnects. Particular emphasis is placed on manipulating the nanowire growth kinetics to produce high aspect ratio structures. The discussion of Pt interconnects focuses on the development of low-resistivity devices and the electrical and structural analysis of those devices. Chapter 1 reviews the most critical aspects of Ge nanowire growth which must be understood before they can be integrated into future nanodevices. These features include the synthetic methods employed to grow Ge nanowires, the kinetic and thermodynamic aspects of their growth and nanowire morphology control. Chapter 2 outlines the experimental methods used to synthesise and characterise Ge nanowires as well as the methods used to fabricate and analyse Pt interconnects. Chapter 3 discusses the control of Ge nanowire growth kinetics via the manipulation of the supersaturation of Ge in the Au/Ge binary alloy system. This is accomplished through the use of bi-layer films, which pre-form Au/Ge alloy catalysts before the introduction of the Ge precursor. The growth from these catalysts is then compared with Ge nanowire growth from standard elemental Au seeds. Nanowires grown from pre-formed Au/Ge alloy seeds demonstrate longer lengths and higher growth rates than those grown from standard Au seeds. In-situ TEM heating on the Au/Ge bi-layer films is used to support the growth characteristics observed. Chapter 4 extends the work of chapter 3 by utilising Au/Ag/Ge tri-layer films to enhance the growth rates and lengths of Ge nanowires. These nanowires are grown from Au/Ag/Ge ternary alloy catalysts. Once again, the supersaturation is influenced, only this time it is through the simultaneous manipulation of both the solute concentration and equilibrium concentration of Ge in the Au/Ag/Ge ternary alloy system. The introduction of Ag to the Au/Ge binary alloy lowers the equilibrium concentration, thus increasing the nanowire growth rate and length. Nanowires with uniform diameters were obtained via synthesis from AuxAg1-x alloy nanoparticles. Manifestation of the Gibbs-Thomson effect, resulting from the dependence of the mean nanowire length as a function of diameter, was observed for all of the nanowires grown from the AuxAg1-x nanoparticles. Finally, in-situ TEM heating was used to support the nanowire growth characteristics. Chapter 5 details the fabrication and characterisation of Pt interconnects deposited by electron beam induced deposition of two different precursors. The fabrication is conducted inside a dual beam FIB. The electrical and structural characteristics of interconnects deposited from a standard organometallic precursor and a novel carbon-free precursor are compared. The electrical performance of the carbon-free interconnects is shown to be superior to that of the organometallic devices and this is correlated to the structural composition of both interconnects via in-situ TEM heating and HAADF-STEM analysis. Annealing of the interconnects is carried out under two different atmospheres in order to reduce the electrical resistivity even further. Finally, chapter 6 presents some important conclusions and summarises each of the previous chapters.

First principles simulation of amorphous silicon bulk, interfaces, and nanowires for photovoltaics

Amorphous silicon has become the material of choice for many technologies, with major applications in large area electronics: displays, image sensing and thin film photovoltaic cells. This technology development has occurred because amorphous silicon is a thin film semiconductor that can be deposited on large, low cost substrates using low temperature. In this thesis, classical molecular dynamics and first principles DFT calculations have been performed to generate structural models of amorphous and hydrogenated amorphous silicon and interfaces of amorphous and crystalline silicon, with the ultimate aim of understanding the photovoltaic properties of core-shell crystalline amorphous Si nanowire structures. We have shown, unexpectedly, from the simulations, that our understanding of hydrogenated bulk a-Si needs to be revisited, with our robust finding that when fully saturated with hydrogen, bulk a-Si exhibits a constant optical energy gap, irrespective of the hydrogen concentration in the sample. Unsaturated a-Si:H, with a lower than optimum hydrogen content, shows a smaller optical gap, that increases with hydrogen content until saturation is reached. The mobility gaps obtained from an analysis of the electronic states show similar behavior. We also obtained that the optical and mobility gaps show a volcano curve as the H content is varied from 7% (undersaturation) to 18% (mild oversaturation). In the case of mild over saturation, the mid-gap states arise exclusively from an increase in the density of strained Si-Si bonds. Analysis of our structures shows the extra H atoms in this case form a bridge between neighboring silicon atoms which increases the corresponding Si-Si distance and promotes bond length disorder in the sample. That has the potential to enhance the Staebler-Wronski effect. Planar interface models of amorphous-crystalline silicon have been generated in Si (100), (110) and (111) surfaces. The interface models are characterized by structure, RDF, electronic density of states and optical absorption spectrum. We find that the least stable (100) surface will result in the formation of the thickest amorphous silicon layer, while the most stable (110) surface forms the smallest amorphous region. We calculated for the first time band offsets of a-Si:H/c-Si heterojunctions from first principles and examined the influence of different surface orientations and amorphous layer thickness on the offsets and implications for device performance. The band offsets depend on the amorphous layer thickness and increase with thickness. By controlling the amorphous layer thickness we can potentially optimise the solar cell parameters. Finally, we have successfully generated different amorphous layer thickness of the a-Si/c-Si and a-Si:H/c-Si 5 nm nanowires from heat and quench. We perform structural analysis of the a-Si-/c-Si nanowires. The RDF, Si-Si bond length distributions, and the coordination number distributions of amorphous regions of the nanowires reproduce similar behaviour compared to bulk amorphous silicon. In the final part of this thesis we examine different surface terminating chemical groups, -H, - OH and –NH2 in (001) GeNW. Our work shows that the diameter of Ge nanowires and the nature of surface terminating groups both play a significant role in both the magnitude and the nature of the nanowire band gaps, allowing tuning of the band gap by up to 1.1 eV. We also show for the first time how the nanowire diameter and surface termination shifts the absorption edge in the Ge nanowires to longer wavelengths. Thus, the combination of nanowire diameter and surface chemistry can be effectively utilised to tune the band gaps and thus light absorption properties of small diameter Ge nanowires.

Non-equilibrium induction of tin in germanium: towards direct bandgap Ge1-xSnx nanowires

The development of non-equilibrium group IV nanoscale alloys is critical to achieving new functionalities, such as the formation of a direct bandgap in a conventional indirect bandgap elemental semiconductor. Here, we describe the fabrication of uniform diameter, direct bandgap Ge1-xSnx alloy nanowires, with a Sn incorporation up to 9.2[thinsp]at.%, far in excess of the equilibrium solubility of Sn in bulk Ge, through a conventional catalytic bottom-up growth paradigm using noble metal and metal alloy catalysts. Metal alloy catalysts permitted a greater inclusion of Sn in Ge nanowires compared with conventional Au catalysts, when used during vapour-liquid-solid growth. The addition of an annealing step close to the Ge-Sn eutectic temperature (230[thinsp][deg]C) during cool-down, further facilitated the excessive dissolution of Sn in the nanowires. Sn was distributed throughout the Ge nanowire lattice with no metallic Sn segregation or precipitation at the surface or within the bulk of the nanowires. The non-equilibrium incorporation of Sn into the Ge nanowires can be understood in terms of a kinetic trapping model for impurity incorporation at the triple-phase boundary during growth.

Modifying the band gap and optical properties of Germanium nanowires by surface termination

Semiconductor nanowires, based on silicon (Si) or germanium (Ge) are leading candidates for many ICT applications, including next generation transistors, optoelectronics, gas and biosensing and photovoltaics. Key to these applications is the possibility to tune the band gap by changing the diameter of the nanowire. Ge nanowires of different diameter have been studied with H termination, but, using ideas from chemistry, changing the surface terminating group can be used to modulate the band gap. In this paper we apply the generalised gradient approximation of density functional theory (GGA-DFT) and hybrid DFT to study the effect of diameter and surface termination using –H, –NH2 and –OH groups on the band gap of (001), (110) and (111) oriented germanium nanowires. We show that the surface terminating group allows both the magnitude and the nature of the band gap to be changed. We further show that the absorption edge shifts to longer wavelength with the –NH2 and –OH terminations compared to the –H termination and we trace the origin of this effect to valence band modifications upon modifying the nanowire with –NH2 or –OH. These results show that it is possible to tune the band gap of small diameter Ge nanowires over a range of ca. 1.1 eV by simple surface chemistry.

Metastable crystalline AuGe catalysts formed during isothermal germanium nanowire growth

We observe the formation of metastable AuGe phases without quenching, during strictly isothermal nucleation and growth of Ge nanowires, using video-rate lattice-resolved environmental transmission electron microscopy. We explain the unexpected formation of these phases through a novel pathway involving changes in composition rather than temperature. The metastable catalyst has important implications for nanowire growth, and more broadly, the isothermal process provides both a new approach to growing and studying metastable phases, and a new perspective on their formation. © 2012 American Physical Society.

Semiconductor nanowire fabrication via bottom-up & top-down paradigms

Semiconductor nanowires are pseudo 1-D structures where the magnitude of the semiconducting material is confined to a length of less than 100 nm in two dimensions. Semiconductor nanowires have a vast range of potential applications, including electronic (logic devices, diodes), photonic (laser, photodetector), biological (sensors, drug delivery), energy (batteries, solar cells, thermoelectric generators), and magnetic (spintronic, memory) devices. Semiconductor nanowires can be fabricated by a range of methods which can be categorised into one of two paradigms, bottom-up or top-down. Bottom-up processes can be defined as those where structures are assembled from their sub-components in an additive fashion. Top-down fabrication strategies use sculpting or etching to carve structures from a larger piece of material in a subtractive fashion. This seminar will detail a number of novel routes to fabricate semiconductor nanowires by both bottom-up and top-down paradigms. Firstly, a novel bottom-up route to fabricate Ge nanowires with controlled diameter distributions in the sub-20 nm regime will be described. This route details nanowire synthesis and diameter control in the absence of a foreign seed metal catalyst. Additionally a top-down route to nanowire array fabrication will be detailed outlining the importance of surface chemistry in high-resolution electron beam lithography (EBL) using hydrogen silsesquioxane (HSQ) on Ge and Bi2Se3 surfaces. Finally, a process will be described for the directed self-assembly of a diblock copolymer (PS-b-PDMS) using an EBL defined template. This section will also detail a route toward selective template sidewall wetting of either block in the PS-b-PDMS system, through tailored functionalisation of the template and substrate surfaces.