Nanopartículas de CeO2 modificadas com Er obtidas pelo método hidrotermal microondas: estudo fotoluminescente

The development of nanostructured materials have aroused great interest of the industries all over the country, since they enable the development of devices that can be used as gate insulators on silicon transistors, electrochromic devices, solid electrolyte oxygen sensors and as a photoluminescent materials . In this project, it is proposed to investigate the optical properties of CeO2 modified with rare earth Er processed in hydrothermal-microwave. The synthesis of one-dimensional nanostructures (1D) was measured from dilute aqueous solutions of acids and salts of starting reagents in the presence of chemical basis, after these aqueous solutions were processed on hydrothermal-microwave to particle growth. The particles obtained after processing were characterized by X-ray Diffraction, Rietveld Analysis and Raman Spectroscopy. The particle morphology was observed by scanning electron microscopy with field emission gun. The synthesis of 1D nanostructures are evaluated for different surfactants and starting precursors (ceria different salts), pH, temperature and pressure which can modify the morphology of the nanostructures. Combining laboratory experiments and theoretical calculations it was desired to understand the organization of the nanoparticles and their resulting structure. Strict control of chemical homogeneity, crystal structure, microstructure and interaction of the CeO2 cluster with different surfactants using the Hartree-Fock method, was intended to obtain properties compatible with their use in catalysts and optical devices. The use of mineralizer agent KOH and 8 minutes of processing time synthesis conditions were chosen to evaluate the effect of Er dopant. It has been proved that this doping with rare earth increases the photoluminescent properties of the compound obtained without change the structural and morphological propreties of ceria

Nanopartículas de CeO2 modificadas com Er obtidas pelo método hidrotermal microondas: estudo fotoluminescente

The development of nanostructured materials have aroused great interest of the industries all over the country, since they enable the development of devices that can be used as gate insulators on silicon transistors, electrochromic devices, solid electrolyte oxygen sensors and as a photoluminescent materials . In this project, it is proposed to investigate the optical properties of CeO2 modified with rare earth Er processed in hydrothermal-microwave. The synthesis of one-dimensional nanostructures (1D) was measured from dilute aqueous solutions of acids and salts of starting reagents in the presence of chemical basis, after these aqueous solutions were processed on hydrothermal-microwave to particle growth. The particles obtained after processing were characterized by X-ray Diffraction, Rietveld Analysis and Raman Spectroscopy. The particle morphology was observed by scanning electron microscopy with field emission gun. The synthesis of 1D nanostructures are evaluated for different surfactants and starting precursors (ceria different salts), pH, temperature and pressure which can modify the morphology of the nanostructures. Combining laboratory experiments and theoretical calculations it was desired to understand the organization of the nanoparticles and their resulting structure. Strict control of chemical homogeneity, crystal structure, microstructure and interaction of the CeO2 cluster with different surfactants using the Hartree-Fock method, was intended to obtain properties compatible with their use in catalysts and optical devices. The use of mineralizer agent KOH and 8 minutes of processing time synthesis conditions were chosen to evaluate the effect of Er dopant. It has been proved that this doping with rare earth increases the photoluminescent properties of the compound obtained without change the structural and morphological propreties of ceria

Study of metal oxide-semiconductor capacitors with rf magnetron sputtering TiO(x) and TiO(x)N(y) gate dielectric layer

Metal oxide-semiconductor capacitors with TiO(x) deposited with different O(2) partial pressures (30%, 35%, and 40%) and annealed at 550, 750, and 1000 degrees C were fabricated and characterized. Fourier transform infrared, x-ray near edge spectroscopy, and elipsometry measurements were performed to characterize the TiO(x) films. TiO(x)N(y) films were also obtained by adding nitrogen to the gaseous mixture and physical results were presented. Capacitance-voltage (1 MHz) and current-voltage measurements were utilized to obtain the effective dielectric constant, effective oxide thickness, leakage current density, and interface quality. The results show that the obtained TiO(x) films present a dielectric constant varying from 40 to 170 and a leakage current density (for V(G)=-1 V, for some structures as low as 1 nA/cm(2), acceptable for complementary metal oxide semiconductor circuits fabrication), indicating that this material is a viable, in terms of leakage current density, highk substitute for current ultrathin dielectric layers. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3043537]

Bilayer graphene dual-gate nanodevice: An ab initio simulation

We study the electronic transport properties of a dual-gated bilayer graphene nanodevice via first-principles calculations. We investigate the electric current as a function of gate length and temperature. Under the action of an external electrical field we show that even for gate lengths up 100 angstrom, a nonzero current is exhibited. The results can be explained by the presence of a tunneling regime due the remanescent states in the gap. We also discuss the conditions to reach the charge neutrality point in a system free of defects and extrinsic carrier doping.

Transport in disordered two-dimensional topological insulators

The transport properties of the ""inverted"" semiconductor HgTe-based quantum well, recently shown to be a two-dimensional topological insulator, are studied experimentally in the diffusive regime. Nonlocal transport measurements are performed in the absence of magnetic field, and a large signal due to the edge states is observed. This shows that the edge states can propagate over a long distance, similar to 1 mm, and therefore, there is no difference between local and nonlocal electrical measurements in a topological insulator. In the presence of an in-plane magnetic field a strong decrease of the local resistance and complete suppression of the nonlocal resistance is observed. We attribute this behavior to an in-plane magnetic-field-induced transition from the topological insulator state to a conventional bulk metal state.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single- gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 mu m SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a ""C"" shape of the threshold voltage corresponding with the second peak in the gm curve. (C) 2008 Elsevier Ltd. All rights reserved.

Flatness-based control of a single qubit gate

This work considers the open-loop control problem of steering a two-level quantum system from any initial to any final condition. The model of this system evolves on the state space X = SU(2), having two inputs that correspond to the complex amplitude of a resonant laser field. A symmetry preserving flat output is constructed using a fully geometric construction and quaternion computations. Simulation results of this flatness-based open-loop control are provided.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-a round (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the H D is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any Studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. (C) 2008 Elsevier Ltd. All rights reserved.

Quantum controlled-NOT gate with 'hot' trapped ions

We present a novel method of performing quantum logic gates in trapped ion quantum computers which does not require the ions to be cooled down to the ground state of their vibrational modes, thereby avoiding one of the principal experimental difficulties encountered in realizing this technology. Our scheme employs adiabatic passages and a phase shift conditional on the phonon number state.

Quantum process tomography of a controlled-NOT gate

We demonstrate complete characterization of a two-qubit entangling process-a linear optics controlled-NOT gate operating with coincident detection-by quantum process tomography. We use a maximum-likelihood estimation to convert the experimental data into a physical process matrix. The process matrix allows an accurate prediction of the operation of the gate for arbitrary input states and a calculation of gate performance measures such as the average gate fidelity, average purity, and entangling capability of our gate, which are 0.90, 0.83, and 0.73, respectively.