GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL On the other hand, the impact of the gate dielectric on the GIDL for p-channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed. (C) 2011 Elsevier Ltd. All rights reserved.

Study of high-quality ALD gate dielectrics in radiation sensitive oxide field effect transistors

Radiation dosimetry is crucial in many fields, where the exposure of ionizing radiation must be precisely controlled to avoid health and environmental safety issues. Radiotherapy and radioprotection are two examples in which fast and reliable detectors are needed. Compact and large area wearable detectors are being developed to address real-life radiation dosimetry applications, their ideal properties include flexibility, lightness, and low-cost. This thesis contributed to the development of Radiation sensitive OXide Field Effect Transistors (ROXFETs), which are detectors able to provide fast and real-time radiation read out. ROXFETs are based on thin film transistors fabricated with high-mobility amorphous oxide semiconductor, making them compatible with large area, flexible, and low cost production over plastic substrates. The gate dielectric material has high dielectric constant and high atomic number, which results in high performances and high radiation sensitivity, respectively. The aim of this work was to establish a stable and reliable fabrication process for ROXFETs made with atomic layer deposited gate dielectric. A study on the effect of gate dielectric materials was performed, focusing the attention on the properties of the dielectric-semiconductor interface. Single and multi layer dielectric structures were compared during this work. Furthermore, the effect of annealing temperature was studied. The device performances were tested to understand the underlying physical processes. In this way, it was possible to determine a reliable fabrication procedure and an optimal structure for ROXFETs. An outstanding sensitivity of (65±3)V/Gy was measured in detectors with a bi-layer Ta₂O₅-Al₂O₃ gate dielectric with low temperature annealing performed at 180°C.

Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications

Present work deals with the Preparation and characterization of high-k aluminum oxide thin films by atomic layer deposition for gate dielectric applications.The ever-increasing demand for functionality and speed for semiconductor applications requires enhanced performance, which is achieved by the continuous miniaturization of CMOS dimensions. Because of this miniaturization, several parameters, such as the dielectric thickness, come within reach of their physical limit. As the required oxide thickness approaches the sub- l nm range, SiO 2 become unsuitable as a gate dielectric because its limited physical thickness results in excessive leakage current through the gate stack, affecting the long-term reliability of the device. This leakage issue is solved in the 45 mn technology node by the integration of high-k based gate dielectrics, as their higher k-value allows a physically thicker layer while targeting the same capacitance and Equivalent Oxide Thickness (EOT). Moreover, Intel announced that Atomic Layer Deposition (ALD) would be applied to grow these materials on the Si substrate. ALD is based on the sequential use of self-limiting surface reactions of a metallic and oxidizing precursor. This self-limiting feature allows control of material growth and properties at the atomic level, which makes ALD well-suited for the deposition of highly uniform and conformal layers in CMOS devices, even if these have challenging 3D topologies with high aspect-ratios. ALD has currently acquired the status of state-of-the-art and most preferred deposition technique, for producing nano layers of various materials of technological importance. This technique can be adapted to different situations where precision in thickness and perfection in structures are required, especially in the microelectronic scenario.

Temperature performance of AlGaN/GaN MOS-HEMTs on Si substrates using Gd2O3 as gate dielectric

GaN based high electron mobility transistors have draw great attention due to its potential in high temperature, high power and high frequency applications [1, 2]. However, significant gate leakage current is still one of the issues which need to be solved to improve the performance and reliability of the devices [3]. Several research groups have contributed to solve this problem by using metal–oxide–semiconductor HEMTs (MOSHEMTs), with a thin dielectric layer, such as SiO2 [4], Al2O3 [5], HfO2 [6] and Gd2O3 [7] between the gate and the barrier layer on AlGaN/GaN heterostructures. Gd2O3 has shown low interfacial density of states(Dit) with GaN and a high dielectric constant and low electrical leakage currents [8], thus is considered as a promising candidate for the gate dielectrics on GaN. MOS-HEMTs using Gd2O3 grown by electron-beam heating [7] or molecular beam epitaxy (MBE) [8] on GaN or AlGan/GaN structure have been investigated, but further research is still needed in Gd2O3 based AlGaN/GaN MOSHEMTs.

Amorphous HfO(2) and Hf(1-x)Si(x)O via a melt-and-quench scheme using ab initio molecular dynamics

We have performed ab initio molecular dynamics simulations to generate an atomic structure model of amorphous hafnium oxide (a-HfO(2)) via a melt-and-quench scheme. This structure is analyzed via bond-angle and partial pair distribution functions. These results give a Hf-O average nearest-neighbor distance of 2.2 angstrom, which should be compared to the bulk value, which ranges from 1.96 to 2.54 angstrom. We have also investigated the neutral O vacancy and a substitutional Si impurity for various sites, as well as the amorphous phase of Hf(1-x)Si(x)O(2) for x=0.25, 0375, and 0.5.

Improved effective charge density in MOS capacitors with PECVD SiOxNy dielectric layer obtained at low RF power

In this work SiOxNy films are produced and characterized. Series of samples were deposited by the plasma enhanced chemical vapor deposition (PECVD) technique at low temperatures from silane (SiH4), nitrous oxide (N2O) and helium (He) precursor gaseous mixtures, at different deposition power in order to analyze the effect of this parameter on the films structural properties, on the SiOxNy/Si interface quality and on the SiOxNy effective charge density. In order to compare the film structural properties with the interface (SiOxNy/Si) quality and effective charge density, MOS capacitors were fabricated using these films as dielectric layer. X-ray absorption near-edge spectroscopy (XANES), at the Si-K edge, was utilized to investigate the structure of the films and the material bonding characteristics were analyzed through Fourier transform infrared spectroscopy (FTIR). The MOS capacitors were characterized by low and high frequency capacitance (C-V) measurements, in order to obtain the interface state density (D-it) and the effective charge density (N-ss). An effective charge density linear reduction for decreasing deposition power was observed, result that is attributed to the smaller amount of ions present in the plasma for low RF power. (C) 2008 Elsevier B.V. All rights reserved.

Electrical characterization of poly(amide-imide) for application in organic field effect devices

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Electrical characterization of poly(amide-imide) for application in organic field effect devices

The admittance spectra and current-voltage (I-V) characteristics are reported of metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) capacitors employing cross-linked poly(amide-imide) (c-PAI) as the insulator and poly(3-hexylthiophene) (P3HT) as the active semiconductor. The capacitance of the MIM devices are constant in the frequency range from 10 Hz to 100 kHz, with tan delta values as low as 7 x 10(-3) over most of the range. Except at the lowest voltages, the I-V characteristics are well-described by the Schottky equation for thermal emission of electrons from the electrodes into the insulator. The admittance spectra of the MIS devices displayed a classic Maxwell-Wagner frequency response from which the transverse bulk hole mobility was estimated to be similar to 2 x 10(-5) cm(2) V(-1)s(-1) or similar to 5 x 10(-8) cm(2) V(-1)s(-1) depending on whether or not the surface of the insulator had been treated with hexamethyldisilazane (HMDS) prior to deposition of the P3HT. From the maximum loss observed in admittance-voltage plots, the interface trap density was estimated to be similar to 5 x 10(10) cm(-2) eV(-1) or similar to 9 x 10(10) cm(-2) eV(-1) again depending whether or not the insulator was treated with HMDS. We conclude, therefore, that HMDS plays a useful role in promoting order in the P3HT film as well as reducing the density of interface trap states. Although interposing the P3HT layer between the insulator and the gold electrode degrades the insulating properties of the c-PAI, nevertheless, they remain sufficiently good for use in organic electronic devices. (c) 2012 Elsevier B.V. All rights reserved.

Microwave Plasma Assisted ALD Development for the Deposition of Gate Oxides & ALD of High-k Dielectrics

The semiconductor industry's urge towards faster, smaller and cheaper integrated circuits has lead the industry to smaller node devices. The integrated circuits that are now under volume production belong to 22 nm and 14 nm technology nodes. In 2007 the 45 nm technology came with the revolutionary high- /metal gate structure. 22 nm technology utilizes fully depleted tri-gate transistor structure. The 14 nm technology is a continuation of the 22 nm technology. Intel is using second generation tri-gate technology in 14 nm devices. After 14 nm, the semiconductor industry is expected to continue the scaling with 10 nm devices followed by 7 nm. Recently, IBM has announced successful production of 7 nm node test chips. This is the fashion how nanoelectronics industry is proceeding with its scaling trend. For the present node of technologies selective deposition and selective removal of the materials are required. Atomic layer deposition and the atomic layer etching are the respective techniques used for selective deposition and selective removal. Atomic layer deposition still remains as a futuristic manufacturing approach that deposits materials and lms in exact places. In addition to the nano/microelectronics industry, ALD is also widening its application areas and acceptance. The usage of ALD equipments in industry exhibits a diversi cation trend. With this trend, large area, batch processing, particle ALD and plasma enhanced like ALD equipments are becoming prominent in industrial applications. In this work, the development of an atomic layer deposition tool with microwave plasma capability is described, which is a ordable even for lightly funded research labs.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Analysis of temperature variation influence on the analog performance of 45 degrees rotated triple-gate nMuGFETs

This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45 degrees rotated SOI substrates comparing their performance with standard MuGFETs fabricated without substrate rotation. Different fin widths are studied for temperatures ranging from 250 K up to 400 K. The results of transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and unit-gain frequency are studied. It is observed that the substrate rotation improves the carrier mobility of narrow MuGFETs at any temperature because of the changing in the conduction plane at the sidewalls from (1 1 0) to (1 0 0). For lower temperatures, the improvement of the carrier mobility of rotated MuGFETs is more noticeable as well as the rate of mobility improvement with the temperature decrease is larger. The output conductance is weakly affected by the substrate rotation. Although this improvement in the transconductance of rotated MuGFETs is negligibly transferred to the intrinsic voltage gain, the unity-gain frequency of rotated device is improved due to the larger carrier mobility in the entire range of temperatures studied. (C) 2011 Elsevier Ltd. All rights reserved.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Study of metal oxide-semiconductor capacitors with rf magnetron sputtering TiO(x) and TiO(x)N(y) gate dielectric layer

Metal oxide-semiconductor capacitors with TiO(x) deposited with different O(2) partial pressures (30%, 35%, and 40%) and annealed at 550, 750, and 1000 degrees C were fabricated and characterized. Fourier transform infrared, x-ray near edge spectroscopy, and elipsometry measurements were performed to characterize the TiO(x) films. TiO(x)N(y) films were also obtained by adding nitrogen to the gaseous mixture and physical results were presented. Capacitance-voltage (1 MHz) and current-voltage measurements were utilized to obtain the effective dielectric constant, effective oxide thickness, leakage current density, and interface quality. The results show that the obtained TiO(x) films present a dielectric constant varying from 40 to 170 and a leakage current density (for V(G)=-1 V, for some structures as low as 1 nA/cm(2), acceptable for complementary metal oxide semiconductor circuits fabrication), indicating that this material is a viable, in terms of leakage current density, highk substitute for current ultrathin dielectric layers. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3043537]

Bilayer graphene dual-gate nanodevice: An ab initio simulation

We study the electronic transport properties of a dual-gated bilayer graphene nanodevice via first-principles calculations. We investigate the electric current as a function of gate length and temperature. Under the action of an external electrical field we show that even for gate lengths up 100 angstrom, a nonzero current is exhibited. The results can be explained by the presence of a tunneling regime due the remanescent states in the gap. We also discuss the conditions to reach the charge neutrality point in a system free of defects and extrinsic carrier doping.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved