A study into the impact of introducing Year 5 students to university and electronic engineering

This paper demonstrates the benefits of introducing Year 5 school students to university life, encountering styles of teaching to which they would be otherwise unaccustomed; and the results of a survey conducted both before and after the study visit to determine whether the visit was beneficial to the students in academic terms.

Laboratory focussed learning of core electronic engineering concepts in the first year of an honours degree programme

In common with most universities teaching electronic engineering in the UK, Aston University has seen a shift in the profile of its incoming students in recent years. The educational background of students has moved away from traditional Alevel maths and science and if anything this variation is set to increase with the introduction of engineering diplomas. Another major change to the circumstances of undergraduate students relates to the introduction of tuition fees in 1998 which has resulted in an increased likelihood of them working during term time. This may have resulted in students tending to concentrate on elements of the course that directly provide marks contributing to the degree classification. In the light of these factors a root and branch rethink of the electronic engineering degree programme structures at Aston was required. The factors taken into account during the course revision were:. Changes to the qualifications of incoming students. Changes to the background and experience of incoming students. Increase in overseas students, some with very limited practical experience. Student focus on work directly leading to marks. Modular compartmentalisation of knowledge. The need for provision of continuous feedback on performance We discuss these issues with specific reference to a 40 credit first year electronic engineering course and detail the new course structure and evaluate the effectiveness of the changes. The new approach appears to have been successful both educationally and with regards to student satisfaction. The first cohort of students from the new course will graduate in 2010 and results from student surveys relating particularly to project and design work will be presented at the conference. © 2009 K Sugden, D J Webb and R P Reeves.

EMI issues in modern power electronic systems

Electromagnetic compatibility of power electronic systems becomes an engineering discipline and it should be considered at the beginning stage of a design. Thus, a power electronics design becomes more complex and challenging and it requires a good communication between EMI and Power electronics experts. Three major issues in designing a power electronic system are Losses, EMI and Harmonics. These issues affect system cost, size, efficiency and quality and it is a tradeoff between these factors when we design a power converter.

Power electronics education electronic book (PEEEB)

In this website, you can virtually attend all lectures, tutorials, computer Labs and quizzes and also access to lecture notes.

A class E resonant inverter for use as electronic fluorescent lamp ballast

Class E Resonant Inverters are theoretically capable of delivering any power to a load and achieve 100% efficiency at any frequency of operation. In practice efficiency in the “high 90's” can be achieved into megahertz frequencies regardless of inverter output powers. The topology also allows the manipulation of output power through sub-optimal operation, with a negligible efficiency penalty. The 24W inverter discussed in this paper was specifically designed to harness the benefits, and discuss the shortcomings, of the Class E topology for use in the growing market for portable, battery powered lighting. It exhibits a peak recorded power efficiently of over 98%, and a conservatively measured efficiency of 95% across a range of dimming settings.

The role of laboratory exercises in modern power engineering education at the University of Queensland

The University of Queensland (UQ) has extensive laboratory facilities associated with each course in the undergraduate electrical engineering program. The laboratories include machines and drives, power systems simulation, power electronics and intelligent equipment diagnostics. A number of postgraduate coursework programs are available at UQ and the courses associated with these programs also use laboratories. The machine laboratory is currently being renovated with i-lab style web based experimental facilities, which could be remotely accessed. Senior level courses use independent projects using laboratory facilities and this is found to be very useful to improve students' learning skill. Laboratory experiments are always an integral part of a course. Most of the experiments are conducted in a group of 2-3 students and thesis projects in BE and major projects in ME are always individual works. Assessment is done in-class for the performance and also for the report and analysis.

Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.

Non-linear electronic transport in Pt nanowires deposited by focused ion beam

Electrical transport and structural properties of platinum nanowires, deposited using the focussed ion beam method have been investigated. Energy dispersive X-ray spectroscopy reveals metal-rich grains (atomic composition 31% Pt and 50% Ga) in a largely non-metallic matrix of C, O and Si. Resistivity measurements (15-300 K) reveal a negative temperature coefficient with the room-temperature resistivity 80-300 times higher than that of bulk Pt. Temperature dependent current-voltage characteristics exhibit non-linear behaviour in the entire range investigated. The conductance spectra indicate increasing non-linearity with decreasing temperature, reaching 4% at 15 K. The observed electrical behaviour is explained in terms of a model for inter-grain tunnelling in disordered media, a mechanism that is consistent with the strongly disordered nature of the nanowires observed in the structure and composition analysis.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.