Fault Current Limiter Using YBCO Coated Conductor-The Limiting Factor and Its Recovery Time

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Test of a Modular Fault Current Limiter for 220 V Line Using YBCO Coated Conductor Tapes With Shunt Protection

A modular superconducting fault current limiter (SFCL) consisting of 16 elements was constructed and tested in a 220 V line for a fault current between 1 kA to 7.4 kA. The elements are made up of second generation (2G) YBCO-coated conductor tapes with stainless steel reinforcement. For each element four tapes were electrically connected in parallel with effective length of 0.4 m per element, totaling 16 elements connected in series. The evaluation of SFCL performance was carried out under DC and AC tests. The DC test was performed through pulsed current tests and its recovery characteristics under load current were analysed by changing the shunt resistor value. The AC test performed using a 3 MVA/220 V/60 Hz transformer has shown the current limiting ratio achieved a factor higher than 10 during fault of up to five cycles without conductor degradation. The measurement of the voltage for each element during the AC test showed that in this modular SFCL the quench is homogeneous and the transition occurs similarly in all the elements.

Microcontroller-based peak current mode control using digital slope compensation

Microcontroller-based peak current mode control of a buck converter is investigated. The new solution uses a discrete time controller with digital slope compensation. This is implemented using only a single-chip microcontroller to achieve desirable cycle-by-cycle peak current limiting. The digital controller is implemented as a two-pole, two-zero linear difference equation designed using a continuous time model of the buck converter and a discrete time transform. Subharmonic oscillations are removed with digital slope compensation using a discrete staircase ramp. A 16 W hardware implementation directly compares analog and digital control. Frequency response measurements are taken and it is shown that the crossover frequency and expected phase margin of the digital control system match that of its analog counterpart.

Test of a Modular Fault Current Limiter for 220 V Line Using YBCO Coated Conductor Tapes With Shunt Protection

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Fault current limiter using transformer and modular device of YBCO coated conductor

In this work, we report on the evaluation of a superconducting fault current limiter (SFCL). It is consisted of a modular superconducting device combined with a short-circuited transformer with a primary copper winding connected in series to the power line and the secondary side short-circuited by the superconducting device. The basic idea is adding a magnetic component to contribute to the current limitation by the impedance reflected to the line after transition of the superconducting device. The evaluation tests were performed with a prospective current up to 2 kA, with the short-circuited transformer of 2.5 kVA, 220 V/660 V connected to a test facility of 100 kVA power capacity. The resistive SFCL using a modular superconducting device was tested without degradation for a prospective fault current of 1.8 kA, achieving the limiting factor 2.78; the voltage achieved 282 V corresponding to an electric field of 11 V/m. The test performed with the combined SFCL (xsuperconducting device + transformer) using series and toroidal transformers showed current limiting factor of 3.1 and 2 times, respectively. The test results of the combined SFCL with short-circuited transformer showed undesirable influence of the transformer impedance, resulting in reduction of the fault current level. © 2002-2011 IEEE.

Prototype Fault Current Limiter Using Transformer and a Modular Device of YBCO Coated Conductor

A superconducting fault current limiter (SCFL) consisted of a transformer with low reactance connected to the power line and with the secondary winding short-circuited by a modular superconducting limiter device with 16 elements connected in series was constructed and tested. The designed coupling transformer has low dispersion reactance in order to limit the voltage drop in the power line within the range of 5 % to 10 %. The experimental results showed that an insertion of a 0.125 Omega resistance limited the peak current to a factor of 2.5 times of the unlimited current. The power dissipation reached 39 kW during 100 ms, with an energy density of 380 J/cm(3). Based on these results, the SCFL will be further tested in a 3 MVA (15 kV/380 V) generator for currents up to 10 kA.

Converter Supply Transformer For LVDC Distribution System

This master’s thesis is focused on optimizing the parameters of a distribution transformer with respect to low voltage direct current (LVDC) distribution system. One of the main parts of low voltage direct current (LVDC) distribution system is transformer. It is studied from several viewpoints like filtering capabilities of harmonics caused by rectifier, losses and short circuit current limiting Determining available short circuit currents is one of the most important aspects of designing power distribution systems. Short circuits and their effects must be considered in selecting electrical equipment, circuit protection and other devices.

Location of single line-to-ground faults on distribution feeders using voltage measurements

This paper proposes a dedicated algorithm for lation of single line-to-ground faults in distribution systems. The proposed algorithm uses voltage and current phasors measured at the substation level, voltage magnitudes measured at some buses of the feeder, a database containing electrical, operational and topological parameters of the distribution networks, and fault simulation. Voltage measurements can be obtained using power quality devices already installed on the feeders or using voltage measurement devices dedicated for fault location. Using the proposed algorithm, likely faulted points that are located on feeder laterals geographically far from the actual faulted point are excluded from the results. Assessment of the algorithm efficiency was carried out using a 238 buses real-life distribution feeder. The results show that the proposed algorithm is robust for performing fast and efficient fault location for sustained single line-to-ground faults requiring less than 5% of the feeder buses to be covered by voltage measurement devices. © 2006 IEEE.

Electrical Power Distribution System modeling with VHDL-AMS for the construction of a Real-Time Digital Simulator using FPGAS devices

This paper presents a distribution feeder simulation using VHDL-AMS, considering the standard IEEE 13 node test feeder admitted as an example. In an electronic spreadsheet all calculations are performed in order to develop the modeling in VHDL-AMS. The simulation results are compared in relation to the results from the well knowing MatLab/Simulink environment, in order to verify the feasibility of the VHDL-AMS modeling for a standard electrical distribution feeder, using the software SystemVision™. This paper aims to present the first major developments for a future Real-Time Digital Simulator applied to Electrical Power Distribution Systems. © 2012 IEEE.

An efficient implementation of tabu search in feeder reconfiguration of distribution systems

This paper presents an efficient tabu search algorithm (TSA) to solve the problem of feeder reconfiguration of distribution systems. The main characteristics that make the proposed TSA particularly efficient are a) the way in which the neighborhood of the current solution was defined; b) the way in which the objective function value was estimated; and c) the reduction of the neighborhood using heuristic criteria. Four electrical systems, described in detail in the specialized literature, were used to test the proposed TSA. The result demonstrate that it is computationally very fast and finds the best solutions known in the specialized literature. © 2012 IEEE.

Flash-Sintering and Characterization of La0.8Sr0.2Ga0.8Mg0.2O3-δ Electrolytes for Solid Oxide Fuel Cells

La_0.8Sr_0.2Ga_0.8Mg_0.2O_3-δ (LSGM), a promising electrolyte material for intermediate temperature solid oxide fuel cells, can be sintered to a fully dense state by a flash-sintering technique. In this work, LSGM is sintered by the current-limiting flash-sintering process at 690°C under an electric field of 100 V cm^-1, in comparison with up to 1400°C or even higher temperature in conventional furnace sintering. The resultant LSGM samples are investigated by scanning electron microscopy, X-ray diffraction, and electrochemical impedance spectroscopy. The SEM images exhibit well-densified microstructures while XRD results show that the perovskite structure after flash-sintering does not changed. EIS results show that the conductivity of LSGM sintered by the current-limiting flash-sintering process increases with sintering current density value. The conductivity of samples sintered at 120 mA mm^-2 reaches 0.049 σ cm^-1 at 800°C, which is approximate to the value of conventional sintered LSGM samples at 1400°C. Additionally, the flash-sintering process is interpreted by Joule heating theory. Therefore, the current-limiting flash-sintering technique is proved to be an energy-efficient and eligible approach for the densification of LSGM and other materials requiring high sintering temperature.

Fabrication and Pseudo-Analog Characteristics of Ta2O5 -Based ReRAM Cell

Memristori on yksi elektroniikan peruskomponenteista vastuksen, kondensaattorin ja kelan lisäksi. Se on passiivinen komponentti, jonka teorian kehitti Leon Chua vuonna 1971. Kesti kuitenkin yli kolmekymmentä vuotta ennen kuin teoria pystyttiin yhdistämään kokeellisiin tuloksiin. Vuonna 2008 Hewlett Packard julkaisi artikkelin, jossa he väittivät valmistaneensa ensimmäisen toimivan memristorin. Memristori eli muistivastus on resistiivinen komponentti, jonka vastusarvoa pystytään muuttamaan. Nimens mukaisesti memristori kykenee myös säilyttämään vastusarvonsa ilman jatkuvaa virtaa ja jännitettä. Tyypillisesti memristorilla on vähintään kaksi vastusarvoa, joista kumpikin pystytään valitsemaan syöttämällä komponentille jännitettä tai virtaa. Tämän vuoksi memristoreita kutsutaankin usein resistiivisiksi kytkimiksi. Resistiivisiä kytkimiä tutkitaan nykyään paljon erityisesti niiden mahdollistaman muistiteknologian takia. Resistiivisistä kytkimistä rakennettua muistia kutsutaan ReRAM-muistiksi (lyhenne sanoista resistive random access memory). ReRAM-muisti on Flash-muistin tapaan haihtumaton muisti, jota voidaan sähköisesti ohjelmoida tai tyhjentää. Flash-muistia käytetään tällä hetkellä esimerkiksi muistitikuissa. ReRAM-muisti mahdollistaa kuitenkin nopeamman ja vähävirtaiseman toiminnan Flashiin verrattuna, joten se on tulevaisuudessa varteenotettava kilpailija markkinoilla. ReRAM-muisti mahdollistaa myös useammin bitin tallentamisen yhteen muistisoluun binäärisen (”0” tai ”1”) toiminnan sijaan. Tyypillisesti ReRAM-muistisolulla on kaksi rajoittavaa vastusarvoa, mutta näiden kahden tilan välille pystytään mahdollisesti ohjelmoimaan useampia tiloja. Muistisoluja voidaan kutsua analogisiksi, jos tilojen määrää ei ole rajoitettu. Analogisilla muistisoluilla olisi mahdollista rakentaa tehokkaasti esimerkiksi neuroverkkoja. Neuroverkoilla pyritään mallintamaan aivojen toimintaa ja suorittamaan tehtäviä, jotka ovat tyypillisesti vaikeita perinteisille tietokoneohjelmille. Neuroverkkoja käytetään esimerkiksi puheentunnistuksessa tai tekoälytoteutuksissa. Tässä diplomityössä tarkastellaan Ta2O5 -perustuvan ReRAM-muistisolun analogista toimintaa pitäen mielessä soveltuvuus neuroverkkoihin. ReRAM-muistisolun valmistus ja mittaustulokset käydään läpi. Muistisolun toiminta on harvoin täysin analogista, koska kahden rajoittavan vastusarvon välillä on usein rajattu määrä tiloja. Tämän vuoksi toimintaa kutsutaan pseudoanalogiseksi. Mittaustulokset osoittavat, että yksittäinen ReRAM-muistisolu kykenee binääriseen toimintaan hyvin. Joiltain osin yksittäinen solu kykenee tallentamaan useampia tiloja, mutta vastusarvoissa on peräkkäisten ohjelmointisyklien välillä suurta vaihtelevuutta, joka hankaloittaa tulkintaa. Valmistettu ReRAM-muistisolu ei sellaisenaan kykene toimimaan pseudoanalogisena muistina, vaan se vaati rinnalleen virtaa rajoittavan komponentin. Myös valmistusprosessin kehittäminen vähentäisi yksittäisen solun toiminnassa esiintyvää varianssia, jolloin sen toiminta muistuttaisi enemmän pseudoanalogista muistia.

Fault current test of a bifilar Bi-2212 bulk coil

A bifilar Bi-2212 bulk coil with parallel shunt resistor was tested under fault current condition using a 3 MVA single-phase transformer in a 220 V-60 Hz line achieving fault current peak of 8 kA. The fault current tests are performed from steady state peak current of 200 A by applying controlled short circuits up to 8 kA varying the time period from one to six cycles. The test results show the function of the shunt resistor providing homogeneous quench behavior of the HTS coil besides its intrinsic stabilizing role. The limiting current ratio achieves a factor 4.2 during 5 cycles without any degradation.

Electron beam current loss at the high-vacuum-high-pressure boundary in the environmental scanning electron microscope

A significant loss in electron probe current can occur before the electron beam enters the specimen chamber of an environmental scanning electron microscope (ESEM). This loss results from electron scattering in a gaseous jet formed inside and downstream (above) the pressure-limiting aperture (PLA), which separates the high-pressure and high-vacuum regions of the microscope. The electron beam loss above the PLA has been calculated for three different ESEMs, each with a different PLA geometry: an ElectroScan E3, a Philips XL30 ESEM, and a prototype instrument. The mass thickness of gas above the PLA in each case has been determined by Monte Carlo simulation of the gas density variation in the gas jet. It has been found that the PLA configurations used in the commercial instruments produce considerable loss in the electron probe current that dramatically degrades their performance at high chamber pressure and low accelerating voltage. These detrimental effects are minimized in the prototype instrument, which has an optimized thin-foil PLA design.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.