957 resultados para Circuit description


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The electrochemical properties of the film-covered anode/solution interface in the magnesium/ manganese dioxide dry cell have been evaluated. The most plausible electrical equivalent circuit description of the Mg/solution interface with the passive film intact, has been identified. These results are based on the analysis of ac impedance and voltage transient measurements made on the dry cell under conditions which cause no damage to the protective passive film on the anode. The study demonstrates the complementary character of impedance and transient measurements when widely different frequency ranges are sampled in each type of investigation. The values and temperature dependence of the anode-film resistance, film capacitance, double-layer capacitance and charge-transfer resistance of the film-covered magnesium/solution interface have been determined. The magnitude of these values and its implications in understanding the important performance aspects of the magnesium/manganese dioxide dry cell are discussed. The study may be extended, in principle, to Li, Al and Ca batteries.

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The electrochemical properties of the film-covered anode/solution interface in the magnesium/ manganese dioxide dry cell have been evaluated. The most plausible electrical equivalent circuit description of the Mg/solution interface with the passive film intact, has been identified. These results are based on the analysis of ac impedance and voltage transient measurements made on the dry cell under conditions which cause no damage to the protective passive film on the anode. The study demonstrates the complementary character of impedance and transient measurements when widely different frequency ranges are sampled in each type of investigation. The values and temperature dependence of the anode-film resistance, film capacitance, double-layer capacitance and charge-transfer resistance of the film-covered magnesium/solution interface have been determined. The magnitude of these values and its implications in understanding the important performance aspects of the magnesium/manganese dioxide dry cell are discussed. The study may be extended, in principle, to Li, Al and Ca batteries.

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This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) setting design for testability in the context of test generation (TG), (2) using failures during FG to focus on testability problems, and (3) relating circuit modifications directly to the failures. A natural functionality set is used to represent the maximum functionalities that a component can have. The current implementation has only primitive domain knowledge and needs other work as well. However, armed with the knowledge of TG, it has already demonstrated its ability and produced some interesting results on a simple microprocessor.

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Electrochemical analyses on confined electroactive molecular layers, herein exemplified with electroactive self-assembled monolayers, sample current contributions that are significantly influenced by additional nonfaradaic and uncompensated resistance effects that, though unresolved, can strongly distort redox analysis. Prior work has shown that impedance-derived capacitance spectroscopy approaches can cleanly resolve all contributions generated at such films, including those which are related to the layer dipolar/electrostatic relaxation characteristics. We show herein that, in isolating the faradaic and nonfaradaic contributions present within an improved equivalent circuit description of such interfaces, it is possible to accurately simulate subsequently observed cyclic voltammograms (that is, generated current versus potential patterns map accurately onto frequency domain measurements). Not only does this enable a frequency-resolved quantification of all components present, and in so doing, a full validation of the equivalent circuit model utilized, but also facilitates the generation of background subtracted cyclic voltammograms remarkably free from all but faradaic contributions. © 2012 American Chemical Society.

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Computer aided design of Monolithic Microwave Integrated Circuits (MMICs) depends critically on active device models that are accurate, computationally efficient, and easily extracted from measurements or device simulators. Empirical models of active electron devices, which are based on actual device measurements, do not provide a detailed description of the electron device physics. However they are numerically efficient and quite accurate. These characteristics make them very suitable for MMIC design in the framework of commercially available CAD tools. In the empirical model formulation it is very important to separate linear memory effects (parasitic effects) from the nonlinear effects (intrinsic effects). Thus an empirical active device model is generally described by an extrinsic linear part which accounts for the parasitic passive structures connecting the nonlinear intrinsic electron device to the external world. An important task circuit designers deal with is evaluating the ultimate potential of a device for specific applications. In fact once the technology has been selected, the designer would choose the best device for the particular application and the best device for the different blocks composing the overall MMIC. Thus in order to accurately reproducing the behaviour of different-in-size devices, good scalability properties of the model are necessarily required. Another important aspect of empirical modelling of electron devices is the mathematical (or equivalent circuit) description of the nonlinearities inherently associated with the intrinsic device. Once the model has been defined, the proper measurements for the characterization of the device are performed in order to identify the model. Hence, the correct measurement of the device nonlinear characteristics (in the device characterization phase) and their reconstruction (in the identification or even simulation phase) are two of the more important aspects of empirical modelling. This thesis presents an original contribution to nonlinear electron device empirical modelling treating the issues of model scalability and reconstruction of the device nonlinear characteristics. The scalability of an empirical model strictly depends on the scalability of the linear extrinsic parasitic network, which should possibly maintain the link between technological process parameters and the corresponding device electrical response. Since lumped parasitic networks, together with simple linear scaling rules, cannot provide accurate scalable models, either complicate technology-dependent scaling rules or computationally inefficient distributed models are available in literature. This thesis shows how the above mentioned problems can be avoided through the use of commercially available electromagnetic (EM) simulators. They enable the actual device geometry and material stratification, as well as losses in the dielectrics and electrodes, to be taken into account for any given device structure and size, providing an accurate description of the parasitic effects which occur in the device passive structure. It is shown how the electron device behaviour can be described as an equivalent two-port intrinsic nonlinear block connected to a linear distributed four-port passive parasitic network, which is identified by means of the EM simulation of the device layout, allowing for better frequency extrapolation and scalability properties than conventional empirical models. Concerning the issue of the reconstruction of the nonlinear electron device characteristics, a data approximation algorithm has been developed for the exploitation in the framework of empirical table look-up nonlinear models. Such an approach is based on the strong analogy between timedomain signal reconstruction from a set of samples and the continuous approximation of device nonlinear characteristics on the basis of a finite grid of measurements. According to this criterion, nonlinear empirical device modelling can be carried out by using, in the sampled voltage domain, typical methods of the time-domain sampling theory.

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When verifying or reverse-engineering digital circuits, one often wants to identify and understand small components in a larger system. A possible approach is to show that the sub-circuit under investigation is functionally equivalent to a reference implementation. In many cases, this task is difficult as one may not have full information about the mapping between input and output of the two circuits, or because the equivalence depends on settings of control inputs. We propose a template-based approach that automates this process. It extracts a functional description for a low-level combinational circuit by showing it to be equivalent to a reference implementation, while synthesizing an appropriate mapping of input and output signals and setting of control signals. The method relies on solving an exists/forall problem using an SMT solver, and on a pruning technique based on signature computation.

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The Printed Circuit Board (PCB) layout design is one of the most important and time consuming phases during equipment design process in all electronic industries. This paper is concerned with the development and implementation of a computer aided PCB design package. A set of programs which operate on a description of the circuit supplied by the user in the form of a data file and subsequently design the layout of a double-sided PCB has been developed. The algorithms used for the design of the PCB optimise the board area and the length of copper tracks used for the interconnections. The output of the package is the layout drawing of the PCB, drawn on a CALCOMP hard copy plotter and a Tektronix 4012 storage graphics display terminal. The routing density (the board area required for one component) achieved by this package is typically 0.8 sq. inch per IC. The package is implemented on a DEC 1090 system in Pascal and FORTRAN and SIGN(1) graphics package is used for display generation.

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Load commutated inverter (LCI)-fed wound field synchronous motor drives are used for medium-voltage high-power drive applications. This drive suffers from drawbacks such as complex starting procedure, sixth harmonic torque pulsations, quasi square wave motor current, notches in the terminal voltages, etc. In this paper, a hybrid converter circuit, consisting of an LCI and a voltage source inverter (VSI), is proposed, which can be a universal high-power converter solution for wound field synchronous motor drives. The proposed circuit, with the addition of a current-controlled VSI, overcomes nearly all of the shortcomings present in the conventional LCI-based system besides providing many additional advantages. In the proposed drive, the motor voltage and current are always sinusoidal even with the LCI switching at the fundamental frequency. The performance of the drive is demonstrated with detailed experimental waveforms from a 15.8-hp salient pole wound field synchronous machine. Finally, a brief description of the control scheme used for the proposed circuit is given.

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In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

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This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results. © 2006 IEEE.

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A description is given of the global atmospheric electric circuit operating between the Earth’s surface and the ionosphere. Attention is drawn to the huge range of horizontal and vertical spatial scales, ranging from 10−9 m to 1012 m, concerned with the many important processes at work. A similarly enormous range of time scales is involved from 10−6 s to 109 s, in the physical effects and different phenomena that need to be considered. The current flowing in the global circuit is generated by disturbed weather such as thunderstorms and electrified rain/shower clouds, mostly occurring over the Earth’s land surface. The profile of electrical conductivity up through the atmosphere, determined mainly by galactic cosmic ray ionization, is a crucial parameter of the circuit. Model simulation results on the variation of the ionospheric potential, ∼250 kV positive with respect to the Earth’s potential, following lightning discharges and sprites are summarized. Experimental results comparing global circuit variations with the neutron rate recorded at Climax, Colorado, are then discussed. Within the return (load) part of the circuit in the fair weather regions remote from the generators, charge layers exist on the upper and lower edges of extensive layer clouds; new experimental evidence for these charge layers is also reviewed. Finally, some directions for future research in the subject are suggested.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

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This paper presents a configurable architecture which was designed to aid in the simulation of ULSI circuits at the transistor level. Elsewhere [1] this architecture was shown to be able to run such simulations several times as fast as standard circuit simulators such as SPICES. In this paper, after describing the overall idea and the the architecture of the system as a whole, I concentrate on the description of the architecture of the processing elements of the computing array.