2.1 GHz MOS mixer linearisation approach for IIP2 enhancement using multiple factor compensation

An integrated downconversion CMOS mixer incorporating a comprehensive compensation scheme is presented which aims to minimise second-order intermodulation distortion (IMD2). Unlike previously reported IMD2 calibration schemes which tune only one nonlinear factor at a time, the presented solution allows simultaneous adjustment of several different factors thus achieving a better compensation. The mixer has been implemented in UMC 0.18 μm CMOS to verify the proposed scheme and for comparison with alternative compensation methods. Measurements show that the solution described can improve the input intercept point (IIP2) by over 20 dB while maintaining good amplification and noise performance. IMD2 calibration results are presented and show useful advantages over other approaches. To the best of the authors' knowledge, this scheme for IMD2 calibration has not been previously reported. © The Institution of Engineering and Technology 2013.

Differential mixer with NMOS/PMOS stack at switching stage

This paper proposes a novel differential mixer topology. The traditional stage of switching is replaced by a stack of NMOS and PMOS transistors combined. A design is given of a 900 MHz down-conversion mixer using a 0.35 μm CMOS process. Comparison with conventional mixer shows that the topology leads to a better performance in terms of conversion gain and linearity. ©2012 IEEE.

Method to Improve the Linearity of Active Commutating Mixers Using Dynamic Current Injection

A double balanced (DBM) CMOS mixer providing high linearity is presented in this paper. A cross-coupled pair used in the IF stage of the mixer to dynamically inject current into the to mixer provide a high linearity. The proposed DBM was fabricated using a standard 130-nm CMOS process and was tested on-wafer. The double balanced mixer delivers 10 dB conversion gain, 9.5 dBm IIP3, and input P1dB of -2.4 dBm. RF bandwidth of the proposed mixer is 6 GHz, covering 0.5 GHz to 6.5 GHz with IF bandwidth of 300 MHz. RF to IF and LO to IF isolation are also better than 59 dB in the whole frequency band. The circuit uses an area of 0.015 mm2 excluding bonding pads and draw 4.5mW from a 1.2V supply.

A new low-power highly linear mixer design using differential derivative superposition

This paper presents the analysis and design of a new low power and highly linear mixer topology based on a newly reported differential derivative superposition method. Volterra series and harmonic balance are employed to investigate its linearisation mechanism and to optimise the design. A prototype mixer has been designed and is being implemented in 0.18μm CMOS technology. Simulation shows this mixer achieves 19.7dBm IIP3 with 10.5dB conversion gain, 13.2dB noise figure at 2.4GHz and only 3.8mW power consumption. This performance is competitive with already reported mixers.

Enabling Blocks for Integrated CMOS UWB Transceivers

The last decades have seen an unrivaled growth and diffusion of mobile telecommunications. Several standards have been developed to this purposes, from GSM mobile phone communications to WLAN IEEE 802.11, providing different services for the the transmission of signals ranging from voice to high data rate digital communications and Digital Video Broadcasting (DVB). In this wide research and market field, this thesis focuses on Ultra Wideband (UWB) communications, an emerging technology for providing very high data rate transmissions over very short distances. In particular the presented research deals with the circuit design of enabling blocks for MB-OFDM UWB CMOS single-chip transceivers, namely the frequency synthesizer and the transmission mixer and power amplifier. First we discuss three different models for the simulation of chargepump phase-locked loops, namely the continuous time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, a phase noise analysis method based upon the time-domain model is introduced and compared to the results obtained by means of the s-domain model. We compare the three models over the simulation of a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems. In the second part, the theoretical analysis is applied to the design of a 60mW 3.4 to 9.2GHz 12 Bands frequency synthesizer for MB-OFDM UWB based on two wide-band PLLs. The design is presented and discussed up to layout level. A test chip has been implemented in TSMC CMOS 90nm technology, measured data is provided. The functionality of the circuit is proved and specifications are met with state-of-the-art area occupation and power consumption. The last part of the thesis deals with the design of a transmission mixer and a power amplifier for MB-OFDM UWB band group 1. The design has been carried on up to layout level in ST Microlectronics 65nm CMOS technology. Main characteristics of the systems are the wideband behavior (1.6 GHz of bandwidth) and the constant behavior over process parameters, temperature and supply voltage thanks to the design of dedicated adaptive biasing circuits.

Receptores homodinos a 300 GHz basados en tecnología CMOS

Using CMOS transistors for terahertz detection is currently a disruptive technology that offers the direct integration of a terahertz detector with video preamplifiers. The detectors are based on the resistive mixer concept and its performance mainly depends on the following parameters: type of antenna, electrical parameters (gate to drain capacitor and channel length of the CMOS device) and foundry. Two different 300 GHz detectors are discussed: a single transistor detector with a broadband antenna and a differential pair driven by a resonant patch antenna.

300 GHz CMOS video detection using broadband and active planar antennas

Using CMOS transistors for terahertz detection is currently a disruptive technology that offers the direct integration of a terahertz detector with video preamplifiers. The detectors are based on the resistive mixer concept and performance mainly depends on the following parameters: type of antenna, electrical parameters (gate to drain capacitor and channel length of the CMOS device) and foundry. Two different 300 GHz detectors are discussed: a single transistor detector with a broadband antenna and a differential pair driven by a resonant patch antenna.

A Decade-Bandwidth Low-Noise Mixer RFIC with a Distortion-Canceling Output Amplifier

This paper presents a 1-10 GHz low-noise downconvert mixer RFIC suitable for wideband receivers. A switched transconductor mixing core is adopted to reduce noise at high frequencies. By adding a series inductor to the RF transconductor, a flat 4-5 dB noise figure (NF) and a high gain of 26.5 dB can be achieved over a broad bandwidth out to 10 GHz. A CMOS output amplifier is also integrated on-chip, employing derivative superposition (DS) for high linearity and an OIP3 of 16.5 dBm. The circuit consumes less than 20 mW of dc power and occupies an active chip area of less than 0.2 mm2.

State convergence and keyspace reduction of the mixer stream cipher

This paper presents an analysis of the stream cipher Mixer, a bit-based cipher with structural components similar to the well-known Grain cipher and the LILI family of keystream generators. Mixer uses a 128-bit key and 64-bit IV to initialise a 217-bit internal state. The analysis is focused on the initialisation function of Mixer and shows that there exist multiple key-IV pairs which, after initialisation, produce the same initial state, and consequently will generate the same keystream. Furthermore, if the number of iterations of the state update function performed during initialisation is increased, then the number of distinct initial states that can be obtained decreases. It is also shown that there exist some distinct initial states which produce the same keystream, resulting in a further reduction of the effective key space

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.

LPG Gas-Sensing System With SnO2 Thin-Film Transducer and 0.7-mu m CMOS Signal Conditioning ASIC

The design and implementation of a complete gas sensor system for liquified petroleum gas (LPG) gas sensing are presented. The system consists of a SnO2 transducer, a lowcost heater, an application specific integrated circuit (ASIC) with front-end interface circuitry, and a microcontroller interface for data logging. The ASIC includes a relaxation-oscillator-based heater driver circuit that is capable of controlling the sensor operating temperature from 100degC to 425degC. The sensor readout circuit in the ASIC, which is based on the resistance to time conversion technique, has been designed to measure the gas sensor response over three orders of resistance change during its interaction with gases.

Integrated CMOS Gas Sensors

We present a low power gas sensor system on CMOS platform consisting of micromachined polysilicon microheater, temperature controller circuit, resistance readout circuit and SnO2 transducer film. The design criteria for different building blocks of the system is elaborated The microheaters are optimized for temperature uniformity as well as static and dynamic response. The electrical equivalent model for the microheater is derived by extracting thermal and mechanical poles through extensive laser doppler vibrometer measurements. The temperature controller and readout circuit are realized on 130nm CMOS technology The temperature controller re-uses the heater as a temperature sensor and controls the duty cycle of the waveform driving the gate of the power MOSFET which supplies heater current. The readout circuit, with subthreshold operation of the MOSFETs, is based oil resistance to time period conversion followed by frequency to digital converter Subthreshold operatin of MOSFETs coupled with sub-ranging technique, achieves ultra low power consumption with more than five orders of magnitude dynamic range RF sputtered SnO2 film is optimized for its microstructure to achive high sensitivity to sense LPG gas.

Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65mn gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of Response. Surface Methodology (RSM) using Design of Experiments (DOE) and Least Squares Method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by atleast 6X on a normalized basis, against worst case design.

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.