900 resultados para Built-in self-test (BIST)


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Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009)

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The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

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The present research examined the prediction of school students' grades in an upcoming math test via their minimal grade goals (i.e., the minimum grade in an upcoming test one would be satisfied with). Due to its significance for initiating and maintaining goal-directed behavior, self-control capacity was expected to moderate the relation between students' minimal grade goals and their actual grades. Self-control capacity was defined as the dispositional capacity to override or alter one's dominant response tendencies. Prior to a scheduled math test, 172 vocational track students indicated their minimal grade goal for the test and completed a measure of self-control capacity. The test grade was assessed at a second time of measurement. As expected, minimal grade goals more strongly predicted the actual test grades the higher the students' self-control capacity. Implications can be seen in terms of optimizing the prediction and advancement of academic performance.

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Prototype validation is a major concern in modern electronic product design and development. Simulation, structural test, functional and timing debug are all forming parts of the validation process, although very often addressed as dissociated tasks. In this paper we describe an integrated approach to board-level prototype validation, based on a set of mandatory/optional BST instructions and a built-in controller for debug and test, that addresses the late mentioned tasks as inherent parts of a whole process

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The functional method is a new test theory using a new scoring method that assumes complexity in test structure, and thus takes into account every correlation between factors and items. The main specificity of the functional method is to model test scores by multiple regression instead of estimating them by using simplistic sums of points. In order to proceed, the functional method requires the creation of hyperspherical measurement space, in which item responses are expressed by their correlation with orthogonal factors. This method has three main qualities. First, measures are expressed in the absolute metric of correlations; therefore, items, scales and persons are expressed in the same measurement space using the same single metric. Second, factors are systematically orthogonal and without errors, which is optimal in order to predict other outcomes. Such predictions can be performed to estimate how one would answer to other tests, or even to model one's response strategy if it was perfectly coherent. Third, the functional method provides measures of individuals' response validity (i.e., control indices). Herein, we propose a standard procedure in order to identify whether test results are interpretable and to exclude invalid results caused by various response biases based on control indices.

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It is often necessary to selectively attend to important information, at the expense of less important information, especially if you know you cannot remember large amounts of information. The present study examined how younger and older adults select valuable information to study, when given unrestricted choices about how to allocate study time. Participants were shown a display of point values ranging from 1–30. Participants could choose which values to study, and the associated word was then shown. Study time, and the choice to restudy words, was under the participant's control during the 2-minute study session. Overall, both age groups selected high value words to study and studied these more than the lower value words. However, older adults allocated a disproportionately greater amount of study time to the higher-value words, and age-differences in recall were reduced or eliminated for the highest value words. In addition, older adults capitalized on recency effects in a strategic manner, by studying high-value items often but also immediately before the test. A multilevel mediation analysis indicated that participants strategically remembered items with higher point value, and older adults showed similar or even stronger strategic process that may help to compensate for poorer memory. These results demonstrate efficient (and different) metacognitive control operations in younger and older adults, which can allow for strategic regulation of study choices and allocation of study time when remembering important information. The findings are interpreted in terms of life span models of agenda-based regulation and discussed in terms of practical applications. (PsycINFO Database Record (c) 2013 APA, all rights reserved)(journal abstract)

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Objective: To compare results from various tapping tests with diary responses in advanced PD. Background: A home environment test battery for assessing patient state in advanced PD, consisting of diary assessments and motor tests was constructed for a hand computer with touch screen and mobile communication. The diary questions: 1. walking, 2. time in off , on and dyskinetic states, 3. off at worst, 4. dyskinetic at worst, 5. cramps, and 6. satisfied with function, relate to the recent past. Question 7, self-assessment, allows seven steps from -3 ( very off ) to +3 ( very dyskinetic ) and relate to right now. Tapping tests outline: 8. Alternately tapping two fields (un-cued) with right hand 9. Same as 8 but using left hand 10. Tapping an active field (out of two) following a system-generated rhythm (increasing speed) with the dominant hand 11. Tapping an active field (out of four) that randomly changes location when tapped using the dominant hand Methods: 65 patients (currently on Duodopa, or candidates for this treatment) entered diary responses and performed tapping tests four times per day during one to six periods of seven days length. In total there were 224 test periods and 6039 test occasions. Speed for tapping test 10 was discardedand tests 8 and 9 were combined by taking means. Descriptive statistics were used to present the variation of the test variables in relation to self assessment (question 7). Pearson correlation coefficients between speed and accuracy (percent correct) in tapping tests and diary responses were calculated. Results: Mean compliance (percentage completed test occasions per test period) was 83% and the median was 93%. There were large differences in both mean tapping speed and accuracy between the different self-assessed states. Correlations between diary responses and tapping results were small (-0.2 to 0.3, negative values for off-time and dyskinetic-time that had opposite scale directions). Correlations between tapping results were all positive (0.1 to 0.6). Conclusions: The diary responses and tapping results provided different information. The low correlations can partly be explained by the fact that questions related to the past and by random variability, which could be reduced by taking means over test periods. Both tapping speed and accuracy reflect the motor function of the patient to a large extent.

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Current trends in the European Higher Education Area (EHEA) are moving towards the continuous evaluation of the students in substitution of the traditional evaluation based on a single test or exam. This fact and the increase in the number of students during last years in Engineering Schools, requires to modify evaluation procedures making them compatible with the educational and research activities. This work presents a methodology for the automatic generation of questions. These questions can be used as self assessment questions by the student and/or as queries by the teacher. The proposed approach is based on the utilization of parametric questions, formulated as multiple choice questions and generated and supported by the utilization of common programs of data sheets and word processors. Through this approach, every teacher can apply the proposed methodology without the use of programs or tools different from those normally used in his/her daily activity

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Total Ionization Dose (TID) is traditionally measured by radiation sensitive FETs (RADFETs) that require a radiation hardened Analog-to-Digital Converter (ADC) stage. This work introduces a TID sensor based on a delay path whose propagation time is sensitive to the absorbed radiation. It presents the following advantages: it is a digital sensor able to be integrated in CMOS circuits and programmable systems such as FPGAs; it has a configurable sensitivity that allows to use this device for radiation doses ranging from very low to relatively high levels; its interface helps to integrate this sensor in a multidisciplinary sensor network; it is self-timed, hence it does not need a clock signal that can degrade its accuracy. The sensor has been prototyped in a 0.35μm technology, has an area of 0.047mm2, of which 22% is dedicated to measuring radiation, and an energy per conversion of 463pJ. Experimental irradiation tests have validated the correct response of the proposed TID sensor.

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National Highway Traffic Safety Administration, Office of Driver and Pedestrian Programs, Washington, D.C.

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National Highway Traffic Safety Administration, Washington, D.C.

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Background: Self-testing technology allows people to test themselves for chlamydia without professional support. This may result in reassurance and wider access to chlamydia testing, but anxiety could occur on receipt of positive results. This study aimed to identify factors important in understanding self-testing for chlamydia outside formal screening contexts, to explore the potential impacts of self-testing on individuals, and to identify theoretical constructs to form a Framework for future research and intervention development. Methods: Eighteen university students participated in semi-structured interviews; eleven had self-tested for chlamydia. Data were analysed thematically using a Framework approach. Results: Perceived benefits of self-testing included its being convenient, anonymous and not requiring physical examination. There was concern about test accuracy and some participants lacked confidence in using vulvo-vaginal swabs. While some participants expressed concern about the absence of professional support, all said they would seek help on receiving a positive result. Factors identified in Protection Motivation Theory and the Theory of Planned Behaviour, such as response efficacy and self-efficacy, were found to be highly salient to participants in thinking about self-testing. Conclusions: These exploratory findings suggest that self-testing independently of formal health care systems may no more negatively impact people than being tested by health care professionals. Participants’ perceptions about self-testing behaviour were consistent with psychological theories. Findings suggest that interventions which increase confidence in using self-tests and that provide reassurance of test accuracy may increase self-test intentions.

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In this article, the change in examinee effort during an assessment, which we will refer to as persistence, is modeled as an effect of item position. A multilevel extension is proposed to analyze hierarchically structured data and decompose the individual differences in persistence. Data from the 2009 Program of International Student Achievement (PISA) reading assessment from N = 467,819 students from 65 countries are analyzed with the proposed model, and the results are compared across countries. A decrease in examinee effort during the PISA reading assessment was found consistently across countries, with individual differences within and between schools. Both the decrease and the individual differences are more pronounced in lower performing countries. Within schools, persistence is slightly negatively correlated with reading ability; but at the school level, this correlation is positive in most countries. The results of our analyses indicate that it is important to model and control examinee effort in low-stakes assessments. (DIPF/Orig.)