Experimental Study on the Subthreshold Swing of Silicon Nanowire Transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I-ON) and off-current (I-OFF) of the fabricated silicon nanowire FET are 0.59 mu A and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mVN respectively due to the 30 nm thick gate oxide and 1015 cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.

Silicon on silicon : self-organized nanotip arrays formed in reactive Ar+H2 plasmas

The formation of arrays of vertically aligned nanotips on a moderately heated (up to 500 degrees C) Si surface exposed to reactive low-temperature radio frequency (RF) Ar+H(2) plasmas is studied. It is demonstrated that the nanotip surface density, aspect ratio and height dispersion strongly depend on the substrate temperature, discharge power, and gas composition. It is shown that nanotips with aspect ratios from 2.0 to 4.0 can only be produced at a higher RF power density (41.7 mW cm(-3)) and a hydrogen content of about 60%, and that larger aspect ratios can be achieved at substrate temperatures of about 300 degrees C. The use of higher (up to 500 degrees C) temperatures leads to a decrease of the aspect ratio but promotes the formation of more uniform arrays with the height dispersion decreasing to 1.5. At lower (approximately 20 mW cm(-3)) RF power density, only semispherical nanodots can be produced. Based on these experimental results, a nanotip formation scenario is proposed suggesting that sputtering, etching, hydrogen termination, and atom/radical re-deposition are the main concurrent mechanisms for the nanostructure formation. Numerical calculations of the ion flux distribution and hydrogen termination profiles can be used to predict the nanotip shapes and are in a good agreement with the experimental results. This approach can be applied to describe the kinetics of low-temperature formation of other nanoscale materials by plasma treatment.

Process control of cantilever deflection for sensor application based on optical waveguides

This paper reports on the fabrication of cantilever silicon-on-insulator (SOI) optical waveguides and presents solutions to the challenges of using a very thin 260-nm active silicon layer in the SOI structure to enable single-transverse-mode operation of the waveguide with minimal optical transmission losses. In particular, to ameliorate the anchor effect caused by the mean stress difference between the active silicon layer and buried oxide layer, a cantilever flattening process based on Ar plasma treatment is developed and presented. Vertical deflections of 0.5 mu m for 70-mu m-long cantilevers are mitigated to within few nanometers. Experimental investigations of cantilever mechanical resonance characteristics confirm the absence of significant detrimental side effects. Optical and mechanical modeling is extensively used to supplement experimental observations. This approach can satisfy the requirements for on-chip simultaneous readout of many integrated cantilever sensors in which the displacement or resonant frequency changes induced by analyte absorption are measured using an optical-waveguide-based division multiplexed system.

Effect of FIB milling on MEMS SOI cantilevers

Stress induced by Focused Ion Beam (FIB) milling of cantilevers fabricated on silicon-on-insulator (SOI) wafer has been studied. Milling induces stress gradients ranging from -10MPa/μm to -120MPa/μm, depending on the location of cantilevers from the point of milling. Simulations were done to estimate the stress in the milled cantilevers.

Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms. © 2008 IOP Publishing Ltd.

A bulk acoustic mode single-crystal silicon microresonator with a high-quality factor

This paper details a bulk acoustic mode resonator fabricated in single-crystal silicon with a quality factor of 15 000 in air, and over a million below 10 mTorr at a resonant frequency of 2.18 MHz. The resonator is a square plate that is excited in the square-extensional mode and has been fabricated in a commercial foundry silicon-on-insulator (SOI) MEMS process through MEMSCAP. This paper also presents a simple method of extracting resonator parameters from raw measurements heavily buried in electrical feedthrough. Its accuracy has been demonstrated through a comparison between extracted motional resistance values measured at different voltage biases and those predicted from an analytical model. Finally, a method of substantially cancelling electrical feedthrough through system-level electronic implementation is also introduced. © 2008 IOP Publishing Ltd.

Selective metallization on insulator surfaces with femtosecond laser pulses

We report selective metallization on surfaces of insulators ( glass slides and lithium niobate crystal) based on femtosecond laser modification combined with electroless plating. The process is mainly composed of four steps: (1) formation of silver nitrate thin films on the surfaces of glass or crystal substrates; (2) generation of silver particles in the irradiated area by femtosecond laser direct writing; (3) removal of unirradiated silver nitrate films; and (4) selective electroless plating in the modified area. We discuss the mechanism of selective metallization on the insulators. Moreover, we investigate the electrical and adhesive properties of the copper microstructures patterned on the insulator surfaces, showing great potential of integrating electrical functions into lab-on-a-chip devices. (C) 2007 Optical Society of America.

Performance of CMOS Devices in Silicon-on-Sapphire Films After Solid-Phase Epitaxial Growth With Rapid Electron-Beam Heating

The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

REGROWTH RATES OF AMORPHOUS LAYERS IN SILICON-ON-SAPPHIRE FILMS.

The rate and direction of regrowth of amorphous layers, created by self-implantation, in silicon-on-sapphire (SOS) have been studied using time resolved reflectivity (TRR) experiments performed simultaneously at two wavelengths. Regrowth of an amorphous layer towards the surface was observed in specimens implanted with 3 multiplied by (times) 10**1**5Si** plus /cm**2 at 50keV and regrowth of a buried amorphous layer, from a surface seed towards the sapphire, was observed in specimens implanted with 1 multiplied by (times) 10**1**5Si** plus /cm**2 at 175keV. Rapid isothermal heating to regrow the layers was performed in an electron beam annealing system. The combination of 514. 5nm and 632. 8nm wavelengths was found to be particularly useful for TRR studies since the high absorption in amorphous silicon, at the shorter wavelength, means that the TRR trace is not complicated by reflection from the silicon-sapphire interface until regrowth is nearly complete.

Smart chemical sensor application of ZnO nanowires grown on CMOS compatible SOI microheater platform

Smart chemical sensor based on CMOS(complementary metal-oxide- semiconductor) compatible SOI(silicon on insulator) microheater platform was realized by facilitating ZnO nanowires growth on the small membrane at the relatively low temperature. Our SOI microheater platform can be operated at the very low power consumption with novel metal oxide sensing materials, like ZnO or SnO2 nanostructured materials which demand relatively high sensing temperature. In addition, our sol-gel growth method of ZnO nanowires on the SOI membrane was found to be very effective compared with ink-jetting or CVD growth techniques. These combined techniques give us the possibility of smart chemical sensor technology easily merged into the conventional semiconductor IC application. The physical properties of ZnO nanowire network grown by the solution-based method and its chemical sensing property also were reported in this paper.