Engineering of metal oxide nanoparticles for application in electrochemical devices

The growing demand for materials and devices with new functionalities led to the increased inter-est in the field of nanomaterials and nanotechnologies. Nanoparticles, not only present a reduced size as well as high reactivity, which allows the development of electronic and electrochemical devices with exclusive properties, when compared with thin films. This dissertation aims to explore the development of several nanostructured metal oxides by sol-vothermal synthesis and its application in different electrochemical devices. Within this broad theme, this study has a specific number of objectives: a) research of the influence of the synthesis parameters to the structure and morphology of the nanoparticles; b) improvement of the perfor-mance of the electrochromic devices with the application of the nanoparticles as electrode; c) application of the nanoparticles as probes to sensing devices; and d) production of solution-pro-cessed transistors with a nanostructured metal oxide semiconductor. Regarding the results, several conclusions can be exposed. Solvothermal synthesis shows to be a very versatile method to control the growth and morphology of the nanoparticles. The electrochromic device performance is influenced by the different structures and morphologies of WO3 nanoparticles, mainly due to the surface area and conductivity of the materials. The dep-osition of the electrochromic layer by inkjet printing allows the patterning of the electrodes without wasting material and without any additional steps. Nanostructured WO3 probes were produced by electrodeposition and drop casting and applied as pH sensor and biosensor, respectively. The good performance and sensitivity of the devices is explained by the high number of electrochemical reactions occurring at the surface of the na-noparticles. GIZO nanoparticles were deposited by spin coating and used in electrolyte-gated transistors, which promotes a good interface between the semiconductor and the dielectric. The produced transistors work at low potential and with improved ON-OFF current ratio, up to 6 orders of mag-nitude. To summarize, the low temperatures used in the production of the devices are compatible with flexible substrates and additionally, the low cost of the techniques involved can be adapted for disposable devices.

Radiation damage in flexible TFTs and organic detectors

In this thesis was investigated the radiation hardness of the building blocks of a future flexible X-ray sensor system. The characterized building blocks for the pixel addressing and signal amplification electronics are high mobility semiconducting oxide transistors (HMSO-TFTs) and organic transistors (OTFTs), whereas the photonic detection system is based on organic semiconducting single crystals (OSSCs). TFT parameters such as mobility, threshold voltage and subthreshold slope were measured as function of cumulative X-ray dose. Instead for OSSCs conductivity and X-ray sensitivity were analysed after various radiation steps. The results show that ionizing radiation does not lead to degradation in HMSO-TFTs. Instead OTFTs show instability in mobility which is reduced up to 73% for doses of 1 kGy. OSSC demonstrate stable detector properties for the tested total dose range. As conclusion, HMSO-TFTs and OSSCs can be readily employed in the X-ray detector system allowing operation for total doses exceeding 1 kGy of ionizing radiation.

Spray coating of oxide and chalcogenide semiconductor layers for TFT application

This work documents the deposition and optimization of semiconductor thin films using chemical spray coating technique (CSC) for application on thin-film transistors (TFTs), with a low-cost, simple method. CSC setup was implemented and explored for industrial application, within Holst Centre, an R&D center in the Netherlands. As zinc oxide had already been studied within the organization, it was used as a standard material in the initial experiments, obtaining typical mobility values of 0.14 cm2/(V.s) for unpatterned TFTs. Then, oxide X layer characteristics were compared for films deposited with CSC at 40°C and spin-coating. The mobility of the spin-coated TFTs was 103 cm2/(V.s) higher, presumably due to the lack of uniformity of spray-coated film at such low temperatures. Lastly, tin sulfide, a relatively unexplored material, was deposited by CSC in order to obtain functional TFTs and explore the device’s potential for working as a phototransistor. Despite the low mobilities of the devices, a sensitive photodetector was made, showing drain current variation of nearly one order of magnitude under yellow light. CSC technique’s simplicity and versatility was confirmed, as three different semiconductors were successfully implemented into functional devices.

Cellulose-based composites as functional conductive materials for printed electronics

In this work, cellulose-based electro and ionic conductive composites were developed for application in cellulose based printed electronics. Electroconductive inks were successfully formulated for screen-printing using carbon fibers (CFs) and multi-walled carbon nanotubes (MWCNTs) as conductive functional material and cellulose derivatives working as binder. The formulated inks were used to fabricate conductive flexible and disposable electrodes on paper-based substrates. Interesting results were obtained after 10 printing passes and drying at RT of the ink with 10 % wt. of pristine CFs and 3% wt. of carboxymethyl cellulose (CMC), exhibiting a resistivity of 1.03 Ωcm and a resolution of 400 μm. Also, a resistivity of 0.57 Ωcm was obtained for only one printing pass using an ink based on 0.5 % wt. MWCNTs and 3 % wt. CMC. It was also demonstrated that ionic conductive cellulose matrix hydrogel can be used in electrolyte-gated transistors (EGTs). The electrolytes revealed a double layer capacitance of 12.10 μFcm-2 and ionic conductivity of 3.56x10-7 Scm-1. EGTs with a planar configuration, using sputtered GIZO as semiconducting layer, reached an ON/OFF ratio of 3.47x105, a VON of 0.2 V and a charge carrier mobility of 2.32 cm2V-1s-1.

Development of paper transistor with memory effect

This work will discuss the use of different paper membranes as both the substrate and dielectric for field-effect memory transistors. Three different nanofibrillated cellulose membranes (NFC) were used as the dielectric layer of the memory transistors (NFC), one with no additives, one with an added polymer PAE and one with added HCl. Gallium indium zinc oxide (GIZO) was used as the device’s semiconductor and gallium aluminium zinc oxide (GAZO) was used as the gate electrode. Fourier transform infrared spectroscopy (FTIR) was used to access the water content of the paper membranes before and after vacuum. It was found that the devices recovered their water too quickly for a difference to be noticeable in FTIR. The transistor’s electrical performance tests yielded a maximum ION/IOFF ratio of around 3,52x105 and a maximum subthreshold swing of 0,804 V/decade. The retention time of the dielectric charge that grants the transistor its memory capabilities was accessed by the measurement of the drain current periodically during 144 days. During this period the mean drain current did not lower, leaving the retention time of the device indeterminate. These results were compared with similar devices revealing these devices to be at the top tier of the state-of-the-art.

Métodos de extracción de parámetros de un circuito equivalente de pequeña señal para transistores LDMOS de potencia para aplicaciones de RF

En la actualidad, la gran cantidad de aplicaciones que surgen dentro del ámbito de la radiofrecuencia hacen que el desarrollo de dispositivos dentro de este campo sea constante. Estos dispositivos cada vez requieren mayor potencia para frecuencias de trabajo elevadas, lo que sugiere abrir vías de investigación sobre dispositivos de potencia que ofrezcan los resultados deseados para altas frecuencias de operación (GHz). Dentro de este ámbito, el objetivo principal de este proyecto es el de realizar un estudio sobre este tipo de dispositivos, siendo el transistor LDMOS el candidato elegido para tal efecto, debido a su buen comportamiento en frecuencia para tensiones elevadas de funcionamiento.

Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

Analyzing the effects of transient faults into applications

As computer chips implementation technologies evolve to obtain more performance, those computer chips are using smaller components, with bigger density of transistors and working with lower power voltages. All these factors turn the computer chips less robust and increase the probability of a transient fault. Transient faults may occur once and never more happen the same way in a computer system lifetime. There are distinct consequences when a transient fault occurs: the operating system might abort the execution if the change produced by the fault is detected by bad behavior of the application, but the biggest risk is that the fault produces an undetected data corruption that modifies the application final result without warnings (for example a bit flip in some crucial data). With the objective of researching transient faults in computer system’s processor registers and memory we have developed an extension of HP’s and AMD joint full system simulation environment, named COTSon. This extension allows the injection of faults that change a single bit in processor registers and memory of the simulated computer. The developed fault injection system makes it possible to: evaluate the effects of single bit flip transient faults in an application, analyze an application robustness against single bit flip transient faults and validate fault detection mechanism and strategies.

Control de instrumentos mediante el bus GPIB programado con MATLAB

El proyecto que se expone a continuación está dedicado al control de instrumentos mediante el bus de instrumentación GPIB programado con el software Matlab. Está dividido en dos partes. La primera, será llevada a cabo en el laboratorio de docencia y el objetivo será controlar el osciloscopio y el generador de funciones. Como ejemplo del control realizado se desarrollará una aplicación que permitirá obtener el diagrama de Bode de módulo de cualquier sistema electrónico. La segunda parte será llevada a cabo en el laboratorio de investigación y el objetivo será controlar el analizador de semiconductores. En este caso, la aplicación desarrollada permitirá la realización de medidas para la caracterización de transistores. Las aplicaciones de ambas partes estarán realizadas mediante una interfaz gráfica de usuario diseñada con la herramienta GUIDE de Matlab.

Desarrollo de software para el procesado numérico en tarjetas gráficas

Debido al gran número de transistores por mm2 que hoy en día podemos encontrar en las GPU convencionales, en los últimos años éstas se vienen utilizando para propósitos generales gracias a que ofrecen un mayor rendimiento para computación paralela. Este proyecto implementa el producto sparse matrix-vector sobre OpenCL. En los primeros capítulos hacemos una revisión de la base teórica necesaria para comprender el problema. Después veremos los fundamentos de OpenCL y del hardware sobre el que se ejecutarán las librerías desarrolladas. En el siguiente capítulo seguiremos con una descripción del código de los kernels y de su flujo de datos. Finalmente, el software es evaluado basándose en comparativas con la CPU.

Hydrogen-induced changes in the breakdown voltage of InP HEMTs

In this work, electrical measurements show that the breakdown voltage,BVDG, of InP HEMTs increases following exposure to H2. This BVDG shift is nonrecoverable. The increase in BVDG is found to be due to a decrease in the carrier concentration in the extrinsic portion of the device.We provide evidence that H2 reacts with the exposed InAlAs surface in the extrinsic region next to the gate, changing the underlying carrier concentration. Hall measurements of capped and uncapped HEMT samples show that the decrease in sheet carrier concentration can be attributed to a modification of the exposed InAlAs surface. Consistent with this, XPS experiments on uncapped heterostructures give evidence of As loss from the InAlAs surface upon exposure to hydrogen.

Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology

The aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up.

Electrical and optical properties of Zn-In-Sn-O transparent conducting thin films

Indium tin oxide (ITO) is one of the widely used transparent conductive oxides (TCO) for application as transparent electrode in thin film silicon solar cells or thin film transistors owing to its low resistivity and high transparency. Nevertheless, indium is a scarce and expensive element and ITO films require high deposition temperature to achieve good electrical and optical properties. On the other hand, although not competing as ITO, doped Zinc Oxide (ZnO) is a promising and cheaper alternative. Therefore, our strategy has been to deposit ITO and ZnO multicomponent thin films at room temperature by radiofrequency (RF) magnetron co-sputtering in order to achieve TCOs with reduced indium content. Thin films of the quaternary system Zn-In-Sn-O (ZITO) with improved electrical and optical properties have been achieved. The samples were deposited by applying different RF powers to ZnO target while keeping a constant RF power to ITO target. This led to ZITO films with zinc content ratio varying between 0 and 67%. The optical, electrical and morphological properties have been thoroughly studied. The film composition was analysed by X-ray Photoelectron Spectroscopy. The films with 17% zinc content ratio showed the lowest resistivity (6.6 × 10 - 4 Ω cm) and the highest transmittance (above 80% in the visible range). Though X-ray Diffraction studies showed amorphous nature for the films, using High Resolution Transmission Electron Microscopy we found that the microstructure of the films consisted of nanometric crystals embedded in a compact amorphous matrix. The effect of post deposition annealing on the films in both reducing and oxidizing atmospheres were studied. The changes were found to strongly depend on the zinc content ratio in the films.

Optimisation of doped microcrystalline silicon films deposited at very low temperatures by Hot-Wire CVD

In this paper we present new results on doped μc-Si:H thin films deposited by hot-wire chemical vapour deposition (HWCVD) in the very low temperature range (125-275°C). The doped layers were obtained by the addition of diborane or phosphine in the gas phase during deposition. The incorporation of boron and phosphorus in the films and their influence on the crystalline fraction are studied by secondary ion mass spectrometry and Raman spectroscopy, respectively. Good electrical transport properties were obtained in this deposition regime, with best dark conductivities of 2.6 and 9.8 S cm -1 for the p- and n-doped films, respectively. The effect of the hydrogen dilution and the layer thickness on the electrical properties are also studied. Some technological conclusions referred to cross contamination could be deduced from the nominally undoped samples obtained in the same chamber after p- and n-type heavily doped layers.