Effects of breed and production system on lameness parameters in dairy cattle

The aim of the present study was to assess the effects of Holstein-Friesian (HF) and Norwegian (N) dairy cattle genotypes on lameness parameters in dairy cattle within different production systems over the first 2 lactations. Following calving, HF (n = 39) and N (n = 45) heifers were allocated to 1 of 3 systems of production (high level of concentrate, low level of concentrate, and grass-based). High-and low-concentrate animals were continuously housed indoors on a rotational system so that they spent similar amounts of time on slatted and solid concrete floors. Animals on the grass treatment grazed from spring to autumn in both years of the study, so that most animals on this treatment grazed from around peak to late lactation. Claw health was recorded in both hind claws of each animal at 4 observation periods during each lactation as follows: 1) -8 to 70 d postcalving, 2) 71 to 150 d postcalving, 3) 151 to 225 d postcalving, and 4) 226 to 364 d postcalving. Sole lesions, heel erosion, axial wall deviation, sole length of the right lateral hind claw (claw length), right heel width, and right lateral hind heel height were recorded as well as the presence of digital dermatitis. The N cows had lower (better) white line and total lesion scores than HF cows. Cows on the high-and low-concentrate treatments had better sole and total lesion scores than cows on the grass treatment. The HF cows had better locomotion scores than N cows. Breed and production system differences were observed with respect to claw conformation, including claw length, heel width, and heel height. Digital dermatitis was associated with worse sole lesion scores and interacted with production system to influence white line lesion scores and maximum heel erosion scores. This study shows that genetic, environmental, and infectious factors are associated with hoof pathologies in dairy cows.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

NanoStreams: Advancing the Hardware and Software Stack for Real-Time Analytics on Fast Data Streams

NanoStreams is a consortium project funded by the European Commission under its FP7 programme and is a major effort to address the challenges of processing vast amounts of data in real-time, with a markedly lower carbon footprint than the state of the art. The project addresses both the energy challenge and the high-performance required by emerging applications in real-time streaming data analytics. NanoStreams achieves this goal by designing and building disruptive micro-server solutions incorporating real-silicon prototype micro-servers based on System-on-Chip and reconfigurable hardware technologies.

Evaluating Asymmetric Multicore Systems-on-Chip using Iso-Metrics

The end of Dennard scaling has pushed power consumption into a first order concern for current systems, on par with performance. As a result, near-threshold voltage computing (NTVC) has been proposed as a potential means to tackle the limited cooling capacity of CMOS technology. Hardware operating in NTV consumes significantly less power, at the cost of lower frequency, and thus reduced performance, as well as increased error rates. In this paper, we investigate if a low-power systems-on-chip, consisting of ARM's asymmetric big.LITTLE technology, can be an alternative to conventional high performance multicore processors in terms of power/energy in an unreliable scenario. For our study, we use the Conjugate Gradient solver, an algorithm representative of the computations performed by a large range of scientific and engineering codes.

High Strength Thermoplastic Bonding for Multi-channel, Multi-layer Lab-on-Chip Devices for Ocean and Environmental applications

A solvent-vapour thermoplastic bonding process is reported which provides high strength bonding of PMMA over a large area for multi-channel and multi-layer microfluidic devices with shallow high resolution channel features. The bond process utilises a low temperature vacuum thermal fusion step with prior exposure of the substrate to chloroform (CHCl3) vapour to reduce bond temperature to below the PMMA glass transition temperature. Peak tensile and shear bond strengths greater than 3 MPa were achieved for a typical channel depth reduction of 25 µm. The device-equivalent bond performance was evaluated for multiple layers and high resolution channel features using double-side and single-side exposure of the bonding pieces. A single-sided exposure process was achieved which is suited to multi-layer bonding with channel alignment at the expense of greater depth loss and a reduction in peak bond strength. However, leak and burst tests demonstrate bond integrity up to at least 10 bar channel pressure over the full substrate area of 100 mm x 100 mm. The inclusion of metal tracks within the bond resulted in no loss of performance. The vertical wall integrity between channels was found to be compromised by solvent permeation for wall thicknesses of 100 µm which has implications for high resolution serpentine structures. Bond strength is reduced considerably for multi-layer patterned substrates where features on each layer are not aligned, despite the presence of an intermediate blank substrate. Overall a high performance bond process has been developed that has the potential to meet the stringent specifications for lab-on-chip deployment in harsh environmental conditions for applications such as deep ocean profiling.

Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics

The end of Dennard scaling has promoted low power consumption into a firstorder concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, xreliability. These limitations would make them unsuitable for HPC systems and datacenters. In order to demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM’s big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the paper describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.

TINSEL – a web-based intelligent tutoring system on electrical installation design

This paper presents a project consisting on the development of an Intelligent Tutoring System, for training and support concerning the development of electrical installation projects to be used by electrical engineers, technicians and students. One of the major goals of this project is to devise a teaching model based on Intelligent Tutoring techniques, considering not only academic knowledge but also other types of more empirical knowledge, able to achieve successfully the training of electrical installation design.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

Financial impact of introducing the Swiss-DRG reimbursement system on potentially avoidable readmissions at a university hospital.

QUESTION UNDER STUDY: Thirty-day readmissions can be classified as potentially avoidable (PARs) or not avoidable (NARs) by following a specific algorithm (SQLape®). We wanted to assess the financial impact of the Swiss-DRG system, which regroups some readmissions occurring within 18 days after discharge within the initial hospital stay, on PARs at our hospital. METHODS: First, PARs were identified from all hospitalisations recorded in 2011 at our university hospital. Second, 2012 Swiss-DRG readmission rules were applied, regrouped readmissions (RR) were identified, and their financial impact computed. Third, RRs were classified as potentially avoidable (PARRs), not avoidable (NARRs), and others causes (OCRRs). Characteristics of PARR patients and stays were retrieved, and the financial impact of PARRS was computed. RESULTS: A total of 36,777 hospitalisations were recorded in 2011, of which 3,140 were considered as readmissions (8.5%): 1,470 PARs (46.8%) and 1,733 NARs (53.2%). The 2012 Swiss-DRG rules would have resulted in 910 RRs (2.5% of hospitalisations, 29% of readmissions): 395 PARRs (43% of RR), 181 NARRs (20%), and 334 OCRRs (37%). Loss in reimbursement would have amounted to CHF 3.157 million (0.6% of total reimbursement). As many as 95% of the 395 PARR patients lived at home. In total, 28% of PARRs occurred within 3 days after discharge, and 58% lasted less than 5 days; 79% of the patients were discharged home again. Loss in reimbursement would amount to CHF 1.771 million. CONCLUSION: PARs represent a sizeable number of 30-day readmissions, as do PARRs of 18-day RRs in the 2012 Swiss DRG system. They should be the focus of attention, as the PARRs represent an avoidable loss in reimbursement.