Identifying Robust Plans through Plan Diagram Reduction

Estimates of predicate selectivities by database query optimizers often differ significantly from those actually encountered during query execution, leading to poor plan choices and inflated response times. In this paper, we investigate mitigating this problem by replacing selectivity error-sensitive plan choices with alternative plans that provide robust performance. Our approach is based on the recent observation that even the complex and dense "plan diagrams" associated with industrial-strength optimizers can be efficiently reduced to "anorexic" equivalents featuring only a few plans, without materially impacting query processing quality. Extensive experimentation with a rich set of TPC-H and TPC-DS-based query templates in a variety of database environments indicate that plan diagram reduction typically retains plans that are substantially resistant to selectivity errors on the base relations. However, it can sometimes also be severely counter-productive, with the replacements performing much worse. We address this problem through a generalized mathematical characterization of plan cost behavior over the parameter space, which lends itself to efficient criteria of when it is safe to reduce. Our strategies are fully non-invasive and have been implemented in the Picasso optimizer visualization tool.

Efficiently Approximating Query Optimizer Plan Diagrams

Given a parametrized n-dimensional SQL query template and a choice of query optimizer, a plan diagram is a color-coded pictorial enumeration of the execution plan choices of the optimizer over the query parameter space. These diagrams have proved to be a powerful metaphor for the analysis and redesign of modern optimizers, and are gaining currency in diverse industrial and academic institutions. However, their utility is adversely impacted by the impractically large computational overheads incurred when standard brute-force exhaustive approaches are used for producing fine-grained diagrams on high-dimensional query templates. In this paper, we investigate strategies for efficiently producing close approximations to complex plan diagrams. Our techniques are customized to the features available in the optimizer's API, ranging from the generic optimizers that provide only the optimal plan for a query, to those that also support costing of sub-optimal plans and enumerating rank-ordered lists of plans. The techniques collectively feature both random and grid sampling, as well as inference techniques based on nearest-neighbor classifiers, parametric query optimization and plan cost monotonicity. Extensive experimentation with a representative set of TPC-H and TPC-DS-based query templates on industrial-strength optimizers indicates that our techniques are capable of delivering 90% accurate diagrams while incurring less than 15% of the computational overheads of the exhaustive approach. In fact, for full-featured optimizers, we can guarantee zero error with less than 10% overheads. These approximation techniques have been implemented in the publicly available Picasso optimizer visualization tool.

A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

Wave dispersion in a cellular composite with modulated microstructure

In this paper we report a modeling technique and analysis of wave dispersion in a cellular composite laminate with spatially modulated microstructure, which can be modeled by parameterization and homogenization in an appropriate length scale. Higher order beam theory is applied and the system of wave equations are derived. Homogenization of these equations are carried out in the scale of wavelength and frequency of the individual wave modes. Smaller scale scattering below the order of cell size are filtered out in the present approach. The longitudinal dispersion relations for different values of a modulation parameter are analyzed which indicates the existence of stop and pass band patterns. Dispersion relations for flexural-shear case are also analyzed which indicates a tendency toward forming the stop and pass bands for increasing values of a shear stiffness modulation parameter. The effect the phase angle (θ) of the incident wave indicates the existence more number of alternative stop bands and pass bands for θ = 45°.

Design enhancement of the underwater noise control linings through a parsimonious parametric study

Control of sound transmission through the structure and reflection from the structure immersed in fluid media impose highly conflicting requirements on the design of the carpeted noise control linings. These requirements become even more stringent if the structure is expected to be moving with considerable speed particularly under intense hydrostatic pressure. Numerous configurations are possible for designing these linings. Therefore, in this paper, a few lining configurations are identified from the literature for parametric study so that the designer is provided with an environment to analyze and design the lining. A scheme of finite element analysis is used to analyze these linings for their acoustic performance. Commercial finite element software, NISA®, is used as a platform to develop a customized environment wherein design parameters of different configurations can be varied with consistency checks and generate the finite element meshes using the 8-noded hexahedral element. Four types of designs proposed and analysed here address the parameters of interest such as the echo reduction and the transmission loss. Study of the effect of different surface distributions of the cavities is carried out. Effect of static pressure on different designs is reported.