High-current adaptive impedance matching in narrowband power-line communication systems

This paper proposes a high current impedance matching method for narrowband power-line communication (NPLC) systems. The impedance of the power-line channel is time and location variant; therefore, coupling circuitry and the channel are not usually matched. This not only results in poor signal integrity at the receiving end, but also leads to a higher transmission power requirement to secure the communication process. To offset this negative effect, a high-current adaptive impedance circuit to enable impedance matching in power-line networks is reported. The approach taken is to match the channel impedance of N-PLC systems is based on the General Impedance Converter (GIC). In order to achieve high current a special coupler in which the inductive impedance can be altered by adjusting a microcontroller controlled digital resistor is demonstrated. It is shown that the coupler works well with heavy load current in power line networks. It works in both low and high transmitting current modes, a current as high as 760 mA has been obtained. Besides, compared with other adaptive impedance couplers, the advantages include higher matching resolution and a simple control interface. Experimental results are presented to demonstrate the operation of the coupler. © 2011 IEEE.

HVIC switch for high-frequency power converters

A high voltage integrated circuit (HVIC) switch designed as a building block for power converters operating up to 13.56 MHz from off-line voltages is presented. A CMOS-compatible, 500 V power device process is used to integrate control circuitry with a high-speed MOS gate driver and high voltage lateral power MOSFET. Fabrication of the HVIC switches has proceeded in two stages. The first batch of devices showed switching times of less than 5 ns for the power switch and good high frequency performance of a level-shifter for driving half bridge converters. In the second phase, a switch that monolithically integrates all the elements required to form a complete high-frequency converter has been designed.

Optimum Magnetic Circuit Configurations for Permanent Magnet Aerospace Generators

In the design of high-speed low-power electrical generators for unmanned aircraft and spacecraft, maximization of specific output (power/weight) is of prime importance. Several magnetic circuit configurations (radial-field, axial-field, flux-squeezing, homopolar) have been proposed, and in this paper the relative merits of these configurations are subjected to a quantitative investigation over the speed range 10 000–100000 rev/min and power range 250 W-10 kW. The advantages of incorporating new high energy-density magnetic materials are described. Part I deals with establishing an equivalent circuit for permanent-magnet generators. For each configuration the equivalent circuit parameters are related to the physical dimensions of the generator components and an optimization procedure produces a minimum volume design at discrete output powers and operating speeds. The technique is illustrated by a quantitative comparison of the specific outputs of conventional radial-field generators with samarium cobalt and alnico magnets. In Part II the specific outputs of conventional, flux-squeezing, and claw-rotor magnetic circuit configurations are compared. The flux-squeezing configuration is shown to produce the highest specific output for small sizes whereas the conventional configuration is best at large sizes. For all sizes the claw-rotor configuration is significantly inferior. In Part III the power densities available from axial-field and flux-switching magnetic circuit configurations are maximized, over the power range 0.25-10 kW and speed range 10 000–100000 rpm, and compared to the results of Parts I & II. For the axial-field configuration the power density is always less than that of the conventional and flux-squeezing radial-field configurations. For the flux-switching generator, which is able to withstand relatively high mechanical forces in the rotor, the power density is again inferior to the radial-field types, but the difference is less apparent for small (low power, high speed) generator sizes. From the combined results it can be concluded that the flux-squeezing and conventional radial-field magnetic circuit configurations yield designs with minimum volume over the power and speed ranges considered. © 1985, IEEE. All rights reserved.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.

FPGA, physics-based modeling of IGBT and pin diode for hardware co-simulation of complex power electronic converters and systems

This paper presents the steps and the challenges for implementing analytical, physics-based models for the insulated gate bipolar transistor (IGBT) and the PIN diode in hardware and more specifically in field programmable gate arrays (FPGAs). The models can be utilised in hardware co-simulation of complex power electronic converters and entire power systems in order to reduce the simulation time without compromising the accuracy of results. Such a co-simulation allows reliable prediction of the system's performance as well as accurate investigation of the power devices' behaviour during operation. Ultimately, this will allow application-specific optimisation of the devices' structure, circuit topologies as well as enhancement of the control and/or protection schemes.

Design of brushless doubly-fed machines based: On magnetic circuit modeling

This paper proposes a magnetic circuit model (MCM) for the design of a brushless doubly-fed machine (BDFM). The BDFM possesses advantages in terms of high reliability and reduced gearbox stages, and it requires a fractionally-rated power converter. This makes it suitable for utilization in offshore wind turbines. It is difficult for conventional design methods to calculate the flux in the stator because the two sets of stator windings, which have different pole number, form a complex flux pattern which is not easily determined using common analytical approaches. However, it is advantageous to predict the flux density in the teeth and air-gap at the initial design stage for sizing purposes without recourse finite element analysis. Therefore a magnetic circuit model is developed in this paper to calculate the flux density. A BDFM is used as a case study with FEA validation. © 1965-2012 IEEE.

Towards a fast electro-thermo-mechanical IGBT/Diode simulation framework for design of reliable power electronic converters

This paper describes a methodology that enables fast and reasonably accurate prediction of the reliability of power electronic modules featuring IGBTs and p-i-n diodes, by taking into account thermo-mechanical failure mechanisms of the devices and their associated packaging. In brief, the proposed simulation framework performs two main tasks which are tightly linked together: (i) the generation of the power devices' transient thermal response for realistic long load cycles and (ii) the prediction of the power modules' lifetime based on the obtained temperature profiles. In doing so the first task employs compact, physics-based device models, power losses lookup tables and polynomials and combined material-failure and thermal modelling, while the second task uses advanced reliability tests for failure mode and time-to-failure estimation. The proposed technique is intended to be utilised as a design/optimisation tool for reliable power electronic converters, since it allows easy and fast investigation of the effects that changes in circuit topology or devices' characteristics and packaging have on the reliability of the employed power electronic modules. © 2012 IEEE.

An ultra-low power CMOS random number generator

This paper proposes an ultra-low power CMOS random number generator (RING), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 mu m CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 mu W. This novel circuit is a promising unit for low power system and communication applications. (c) 2007 Elsevier Ltd. All rights reserved.

A small signal equivalent circuit model for resonant tunnelling diode

We report a resonant tunneling diode (RTD) small signal equivalent circuit model consisting of quantum capacitance and quantum inductance. The model is verified through the actual InAs/In0.53Ga0.47As/AlAs RTD fabricated on an InP substrate. Model parameters are extracted by fitting the equivalent circuit model with ac measurement data in three different regions of RTD current-voltage (I-V) characteristics. The electron lifetime, representing the average time that the carriers remain in the quasibound states during the tunneling process, is also calculated to be 2.09 ps.

Nanoelectronic Circuit Architectures Based on Single-Electron Turnstiles

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile [1] as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator [2] and the single-electron multiple-valued memories (SEMVs) [3]. The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

Simulation of single electronic device and robust circuit construction

The article mainly focuses on the simulation of the single electron device and circuit. The orthodox model of single electronic device is introduced and the simulation with Matlab and Pspice is illustrated in the article. Moreover, the built of robust circuit using single electronic according to neural network is done and the simulation is also included in the paper. The result shows that neural network added with proper redundancy is an available candidate for single electron device circuit. The proposed structure is also promising for the realization of low ultra-low power consumption and solution of transient device failure.

A Low Power Baseband Chain for CMMB Application

This paper presents experimental results of an analog baseband circuit for China Multimedia Mobile Broadcasting (CMMB) direct conversion receiver in 0.35um SiGe BiCMOS process. It is the first baseband of CMMB RFIC reported so far. A 8(th)-order chebyshev low pass filter (LPF) with calibration system is used in the analog baseband circuit, the filter provides 0.5 dB passband ripple and -35 dB attenuation at 6MHz with the cutoff frequency at 4MHz, the calibration of filter is reported to achieve the bandwidth accuracy of 3%. The baseband variable gain amplifier (VGA) achieves more than 40 dB gain tuning with temperature compensation. In addition, A DC offset cancellation circuit is also introduced to remove the offset from layout and self-mixing, and the remaining offset voltage and current consumption are only 6mV and 412uA respectively. Implemented in a 0.35um SiGe technology with 1.1 mm(2) die size, this tuner baseband achieves OIP3 of 25.5 dBm and dissipate 16.4 mA under 2.8-V supply.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

Combined transparent electrodes for high power GaN-based LEDs with long life time

In this paper fabrication of high power light emitting diodes (LEDs) with combined transparent electrodes on both P-GaN and N-GaN have been demonstrated. Simulation and experimental results show that comparing with traditional metal N electrodes the efficacy of LEDs with transparent N electrode is increased by more than 10% and it is easier in process than the other techniques. Further more, combining the transparent electrodes with dielectric anti-reflection film, the extraction efficiency can be improved by 5%. At the same time, the transparent electrodes were protected by the dielectric film and the reliability of LEDs can be improved.

Design of Low Power Multi-Standard Active-RC Filter for WLAN and DVB-H

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.