The pitfall with PIT tags: Marking freshwater bivalves for translocation induces short-term behavioural costs

Tagging animals is frequently employed in ecological studies to monitor individual behaviour, for example postrelease survival and dispersal of captive-bred animals used in conservation programmes. While the majority of studies focus on the efficacy of tags in facilitating the relocation and identification of individuals, few assess the direct effects of tagging in biasing animal behaviour. We used an experimental approach with a control to differentiate the effects of handling and tagging captive-bred juvenile freshwater pearl mussels, Margaritifera margaritifera, prior to release into the wild. Marking individuals with passive integrated transponder (PIT) tags significantly decreased their burrowing rate and, therefore, increased the time taken to burrow into the substrate. This effect was contributed to, in part, by the detrimental impacts of handling, which also significantly affected activity, burrowing ability and the time taken for each individual to emerge and start probing the substrate. Disturbance during handling and tagging may lead to indirect mortality after release by increasing the risk of predation or dislodgement during flooding, thereby potentially compromising any conservation strategy contingent on population supplementation or reintroduction. This is the first study to demonstrate that handling and PIT tagging has a detrimental impact on invertebrate behaviour. Moreover, our results provide useful information that will inform freshwater bivalve conservation strategies.

A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.