Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing

Análises estatísticas em redes complexas: propriedades topológicas, críticas e dinâmicas

In this thesis, we address two issues of broad conceptual and practical relevance in the study of complex networks. The first is associated with the topological characterization of networks while the second relates to dynamical processes that occur on top of them. Regarding the first line of study, we initially designed a model for networks growth where preferential attachment includes: (i) connectivity and (ii) homophily (links between sites with similar characteristics are more likely). From this, we observe that the competition between these two aspects leads to a heterogeneous pattern of connections with the topological properties of the network showing quite interesting results. In particular, we emphasize that there is a region where the characteristics of sites play an important role not only for the rate at which they get links, but also for the number of connections which occur between sites with similar and dissimilar characteristics. Finally, we investigate the spread of epidemics on the network topology developed, whereas its dissemination follows the rules of the contact process. Using Monte Carlo simulations, we show that the competition between states (infected/healthy) sites, induces a transition between an active phase (presence of sick) and an inactive (no sick). In this context, we estimate the critical point of the transition phase through the cumulant Binder and ratio between moments of the order parameter. Then, using finite size scaling analysis, we determine the critical exponents associated with this transition

Cheaters in mutualism networks

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Static converter: didactic support software

Teaching a course of special electric loads in a continuing education program to power engineers is a difficult task because they are not familiarized with switching topology circuits. Normally, in a typical program, many hours are dedicated to explain the thyristors switching sequence and to draw the converter currents and terminal voltages waveforms for different operative conditions. This work presents teaching support software in order to optimize the time spent in this task and, mainly to benefit the assimilation of the proposed subjects, studying the static converter under different non-ideal operative conditions.

The ZVS-PWM commutation cell applied to the DC-AC converter

This paper presents the analysis of a dc-ac converter using a zero-voltage-switching (ZVS) commutation cell. First, we show the cell applied to the buck converter. The stages of operation are presented along with the main current and voltage equations. Next, we adapt the converter to the regenerative-operation mode. Hence, the full-bridge converter at low-frequency operation is connected in the dc-dc output stage (at high frequency). The main switches commute at zero voltage. The converter operated at constant frequency with pulse-width modulation (PWM), and neither overvoltage nor additional current stress was observed by digital simulation. A design example and experimental results obtained by prototype, rated at 275 V and 1 kW, are also presented. © 1997 IEEE.

Design of a LNA and a Gilbert Cell Mixer MMICs with a GaAs PHEMT technology

The design of a Gilbert Cell Mixer and a low noise amplifier (LNA), using GaAs PHEMT technology is presented. The compatibility is shown for co-integration of both block on the same chip, to form a high performance 1.9 GHz receiver front-end. The designed LNA shows 9.23 dB gain and 2.01 dB noise figure (NF). The mixer is designed to operate at RF=1.9 GHz, LO=2.0 GHz and IF=100 MHz with a gain of 14.3 dB and single sideband noise figure (SSB NF) of 9.6 dB. The mixer presents a bandwith of 8 GHz.

New 12kW three-phase 18-pulse high power factor AC-DC converter with regulated output voltage for rectifier units

This work presents a new high power factor three-phase rectifier based on a Y-connected differential autotransformer with reduced kVA and 18-pulse input current followed by three DC-DC boost converters. The topology provides a regulated output voltage and natural three-phase input power factor correction. The lowest input current harmonic components are the 17th and the 19th. Three boost converters, with constant input currents and regulated parallel connected output voltages are used to process 4kW each one. Analytical results from Fourier analyses of winding currents and the vector diagram of winding voltages are presented. Simulation results to verify the proposed concept and experimental results are shown in the paper.

A high speed 3.3V current mode CMOS comparators with 10-b resolution

This paper presents a high speed current mode CMOS comparator. The comparator was optimized for allows wide range input current 1mA, ±0.5uA resolution and has fast response. This circuit was implemented with 0.8μm CMOS n-well process with area of 120μm × 105μm and operates with 3.3V(±1.65V).

A new three-phase low THD power supply with high-frequency isolation and 60V/200A regulated DC output

This work proposes a new isolated high power factor 12kW power supply based on an 18-pulse transformer arrangement. Three full-bridge converters are used for isolation and to balance the DC-link currents, without current sensing or a current controller. The topology provides a regulated DC output with a very simple control strategy. Simulation and experimental results are presented in this paper.

A linearly-tunable OTA-C sinusoidal oscillator for low-voltage applications

A low-voltage, low-power OTA-C sinusoidal oscillator based on a triode-MOSFET transconductor is here discussed. The classical quadrature model is employed and the transconductor inherent nonlinear characteristic with input voltage is used as the amplitude-stabilization element. An external bias VTUNE linearly adjusts the oscillation frequency. According to a standard 0.8μm CMOS n-well process, a prototype was integrated, with an effective area of 0.28mm2. Experimental data validate the theoretical analysis. For a single 1.8V-supply and 100mV≤VTUNE≤250mV, the oscillation frequency fo ranges from 0.50MHz to 1.125MHz, with a nearly constant gain KVCO=4.16KHz/mV. Maximum output amplitude is 374mVpp @1.12MHz. THD is -41dB @321mVpp. Maximum average consumption is 355μW.

A novel programmable PFC based hybrid rectifier for ultra clean power application

A novel hybrid high power rectifier capable to achieve unity power factor is proposed in this paper. Single-phase SEPIC rectifiers are associated in parallel with each leg of three-phase 6-pulse diode rectifier resulting in a programmable input current waveform structure. In this paper it is described the principles of operation of the proposed converter with detailed simulation and experimental results. For a total harmonic distortion of the input line current (THDI) less than 2% the rated power of the SEPIC rectifiers is 33%. Therefore, power rating of the SEPIC parallel converters is a fraction of the output power, on the range of 20% to 33% of the nominal output power, making the proposed solution economically viable for high power installations, with fast pay back of the investment. Moreover, retrofits to existing installations are also possible with this proposed topology, since the parallel path can be easily controlled by integration with the already existing de-link. Experimental results are presented for a 3 kW implemented prototype, in order to verify the developed analysis.

Programmable PFC based hybrid multipulse power rectifier for utility interface of power electronic converters

In this paper it is proposed a novel hybrid three-phase rectifier capable to achieve high input power factor (PF), and low total harmonic distortion in the input currents (THDI). The proposed hybrid high power rectifier is composed by a standard three-phase 6-pulses diode rectifier (Graetz bridge) with a parallel connection of single-phase Boost rectifiers in each three-phase rectifier leg. Such topology results in a structure capable of programming the input current waveform and providing conditions for obtaining high input power factor and low harmonic current distortion. In order to validate the proposed hybrid rectifier, this paper describes its principles of operation, with detailed experimental results and discussions on power rating of the required Boost converters as related to the desired total harmonic current distortion. It is demonstrated that only a fraction of the output power is processed through the Boost converters, making the proposed solution economically viable for very high power installations, with fast pay back of the investment. Moreover, retrofitting to existing installations is also feasible since the parallel path can be easily controlled by integration with the existing de-link. A prototype rated at 6 kW has been implemented in laboratory and fully demonstrated its operation, performance and feasibility to high power applications. © 2005 IEEE.

An application of CHA to concurrent short-term transmission expansion & reactive power planning

In this paper a heuristic technique for solving simultaneous short-term transmission network expansion and reactive power planning problem (TEPRPP) via an AC model is presented. A constructive heuristic algorithm (CHA) aimed to obtaining a significant quality solution for such problem is employed. An interior point method (IPM) is applied to solve TEPRPP as a nonlinear programming (NLP) during the solution steps of the algorithm. For each proposed network topology, an indicator is deployed to identify the weak buses for reactive power sources placement. The objective function of NLP includes the costs of new transmission lines, real power losses as well as reactive power sources. By allocating reactive power sources at load buses, the circuit capacity may increase while the cost of new lines can be decreased. The proposed methodology is tested on Garver's system and the obtained results shows its capability and the viability of using AC model for solving such non-convex optimization problem. © 2011 IEEE.

Análise e desempenho de redes de acesso sem fio

Pós-graduação em Engenharia Elétrica - FEIS

Sazonalidade e as redes de interações planta-polinizador

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)