An adaptable and scalable asymmetric cryptographic processor

In this paper a novel scalable public-key processor architecture is presented that supports modular exponentiation and Elliptic Curve Cryptography over both prime GF(p) and binary GF(2) extension fields. This is achieved by a high performance instruction set that provides a comprehensive range of integer and polynomial basis field arithmetic. The instruction set and associated hardware are generic in nature and do not specifically support any cryptographic algorithms or protocols. Firmware within the device is used to efficiently implement complex and data intensive arithmetic. A firmware library has been developed in order to demonstrate support for numerous exponentiation and ECC approaches, such as different coordinate systems and integer recoding methods. The processor has been developed as a high-performance asymmetric cryptography platform in the form of a scalable Verilog RTL core. Various features of the processor may be scaled, such as the pipeline width and local memory subsystem, in order to suit area, speed and power requirements. The processor is evaluated and compares favourably with previous work in terms of performance while offering an unparalleled degree of flexibility. © 2006 IEEE.

Learning soft computing control strategies in a modular neural network architecture

Modelling and control of nonlinear dynamical systems is a challenging problem since the dynamics of such systems change over their parameter space. Conventional methodologies for designing nonlinear control laws, such as gain scheduling, are effective because the designer partitions the overall complex control into a number of simpler sub-tasks. This paper describes a new genetic algorithm based method for the design of a modular neural network (MNN) control architecture that learns such partitions of an overall complex control task. Here a chromosome represents both the structure and parameters of an individual neural network in the MNN controller and a hierarchical fuzzy approach is used to select the chromosomes required to accomplish a given control task. This new strategy is applied to the end-point tracking of a single-link flexible manipulator modelled from experimental data. Results show that the MNN controller is simple to design and produces superior performance compared to a single neural network (SNN) controller which is theoretically capable of achieving the desired trajectory. (C) 2003 Elsevier Ltd. All rights reserved.

A modular approach to luminescent dinuclear ruthenium(II) and rhenium(I) complexes

A series of dinuclear (bipyridine)tricarbonylrhenium(I) and tris(bipyridine)ruthenium(II) complexes have been isolated and characterised, bridged by a flexible diamido ethylene glycol chain. A new stepwise synthetic pathway has been investigated to heterometallic complexes, with the rhenium(I) complexes exhibiting an unusual configuration and inequivalence of the metal centres potentially arising from a surprising hydrogen-bonding interaction between an Re–CO group and an amide proton in low-polarity solvents. This interaction appears to be broken by competing hydrogen-bonding species such as dihydrogen phosphate. This effect was not observed in the corresponding ruthenium(II) complexes, which showed very little interaction with anions. The photophysical characterisation shows that the inclusion of two ester/amide groups to the rhenium centre effectively quenches the fluorescence at room temperature. The ruthenium(II) complexes have considerably stronger fluorescence than the rhenium species, and are less affected by theinclusion of ester and amide groups to the 2,2'-bipyridine chelating group.

High-performance IQ modulator-based phase conjugator for modular retrodirective antenna array implementation

In this paper, we verify a new phase conjugating architecture suitable for deployment as (lie core building block in retrodirective antenna arrays, which can be scaled to any number of elements in a modular way without impacting on complexity. Our solution is based on a modified in-phase and quadrature modulator architecture, which completely resolves four major shortcomings of the conventional mixer-based approach currently used for the synthesis of phase conjugated energy derived from a sampled incoming wavefront. 1) The architecture presented removes the need for a local oscillator running at twice the RF signal frequency to be conjugated. 2) It maintains a constant transmit power even if receive power goes as low as -120 dBm. 3) All unwanted re-transmit signal products are suppressed by at least 40 dB. 4) The issue of poor RF-IF leakage prevalent in mixer-based phase-conjugation solutions is completely mitigated. The circuit has also been shown to have high conjugation accuracy (better than +/-1 degrees at -60-dBm input). Near theoretically perfect experimental monostatic and bistatic results are presented for a ten-element retrodirective array constructed using the new phase conjugation architecture.

A Scalable and Programmable Modular Traffic Manager Architecture

A key issue in the design of next generation Internet routers and switches will be provision of traffic manager (TM) functionality in the datapaths of their high speed switching fabrics. A new architecture that allows dynamic deployment of different TM functions is presented. By considering the processing requirements of operations such as policing and congestion, queuing, shaping and scheduling, a solution has been derived that is scalable with a consistent programmable interface. Programmability is achieved using a function computation unit which determines the action (e.g. drop, queue, remark, forward) based on the packet attribute information and a memory storage part. Results of a Xilinx Virtex-5 FPGA reference design are presented.

FPGA montgomery modular multiplication architectures suitable for ECCs over GF(p)

New FPGA architectures for the ordinary Montgomery multiplication algorithm and the FIOS modular multiplication algorithm are presented. The embedded 18×18-bit multipliers and fast carry look-ahead logic located on the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions/subtractions required by these two algorithms. The architectures are developed for use in Elliptic Curve Cryptosystems over GF(p), which require modular field multiplication to perform elliptic curve point addition and doubling. Field sizes of 128-bits and 256-bits are chosen but other field sizes can easily be accommodated, by rapidly reprogramming the FPGA. Overall, the larger the word size of the multiplier, the more efficiently it performs in terms of area/time product. Also, the FIOS algorithm is flexible in that one can tailor the multiplier architecture is to be area efficient, time efficient or a mixture of both by choosing a particular word size. It is estimated that the computation of a 256-bit scalar point multiplication over GF(p) would take about 4.8 ms.