The Lived Experience of Nursing Students With Formative Assessment Formally Embedded in Clinical Courses: A Transcendental Phenomenological Study

The potential of formative assessment (FA) for informing learning in classroom-based nursing courses is clearly established in the literature; however, research on FA in clinical courses remains scarce. This inquiry explored the lived experience of nursing students using transcendental phenomenology and described the phenomenon of being assessed in clinical courses. The research question guiding the study was: How is the phenomenon of assessment experienced by nursing students when FA is formally embedded in clinical courses? Inherent in this question were the following issues: (a) the meaning of clinical experiences for nursing students, (b) the meaning of being assessed through FA, and (c) what it is like to be assessed when FA is formally embedded within clinical experiences. The noematic themes that illuminated the whatness of the participants’ experience were (a) enabled cognitive activity, (b) useful feedback, (c) freedom to be, (d) enhanced focus, (e) stress moderator, and (f) respectful mentorship. The noetic themes associated with how the phenomenon was experienced were related to bodyhood, temporality, spatiality, and relationship to others. The results suggest a fundamental paradigm shift from traditional nursing education to a more pervasive integration of FA in clinical courses so that students have time to learn before being graded on their practice. Furthermore, this inquiry and the literature consulted provide evidence that using cognitive science theory to inform and reform clinical nursing education is a timely option to address the repeated calls from nursing leaders to modernize nursing education. This inquiry contributes to reduce our reliance on assumptions derived from research on FA in nursing classrooms and provides evidence based on the reality of using formative assessment in clinical courses. Recommendations for future research are presented.

SCIL processor : a common intermediate language processor for embedded systems

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Low power optical phase conjugation in dyes embedded in polyvinyl alcohol films

Low power optical phase conjugation in polyvinyl alcohol films embedded with saturable dyes is reported. Phase conjugate reflectivity achieved is higher than that obtained in the case of similar gelatin films.

An Error-Localization, Validation and Optimization Tool for Embedded Code Augmentation: an Architecture Oriented Approach

Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.Embedded systems are usually designed for a single or a specified set of tasks. This specificity means the system design as well as its hardware/software development can be highly optimized. Embedded software must meet the requirements such as high reliability operation on resource-constrained platforms, real time constraints and rapid development. This necessitates the adoption of static machine codes analysis tools running on a host machine for the validation and optimization of embedded system codes, which can help meet all of these goals. This could significantly augment the software quality and is still a challenging field.This dissertation contributes to an architecture oriented code validation, error localization and optimization technique assisting the embedded system designer in software debugging, to make it more effective at early detection of software bugs that are otherwise hard to detect, using the static analysis of machine codes. The focus of this work is to develop methods that automatically localize faults as well as optimize the code and thus improve the debugging process as well as quality of the code.Validation is done with the help of rules of inferences formulated for the target processor. The rules govern the occurrence of illegitimate/out of place instructions and code sequences for executing the computational and integrated peripheral functions. The stipulated rules are encoded in propositional logic formulae and their compliance is tested individually in all possible execution paths of the application programs. An incorrect sequence of machine code pattern is identified using slicing techniques on the control flow graph generated from the machine code.An algorithm to assist the compiler to eliminate the redundant bank switching codes and decide on optimum data allocation to banked memory resulting in minimum number of bank switching codes in embedded system software is proposed. A relation matrix and a state transition diagram formed for the active memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Instances of code redundancy based on the stipulated rules for the target processor are identified.This validation and optimization tool can be integrated to the system development environment. It is a novel approach independent of compiler/assembler, applicable to a wide range of processors once appropriate rules are formulated. Program states are identified mainly with machine code pattern, which drastically reduces the state space creation contributing to an improved state-of-the-art model checking. Though the technique described is general, the implementation is architecture oriented, and hence the feasibility study is conducted on PIC16F87X microcontrollers. The proposed tool will be very useful in steering novices towards correct use of difficult microcontroller features in developing embedded systems.

A Generic Software Architecture for a Domain Specific Distributed Embedded System

In this paper, we have evolved a generic software architecture for a domain specific distributed embedded system. The system under consideration belongs to the Command, Control and Communication systems domain. The systems in such domain have very long operational lifetime. The quality attributes of these systems are equally important as the functional requirements. The main guiding principle followed in this paper for evolving the software architecture has been functional independence of the modules. The quality attributes considered most important for the system are maintainability and modifiability. Architectural styles best suited for the functionally independent modules are proposed with focus on these quality attributes. The software architecture for the system is envisioned as a collection of architecture styles of the functionally independent modules identified

A Compiler Integrated Assistance for Optimum Data Allocation in Banked Memory Embedded Processors

Bank switching in embedded processors having partitioned memory architecture results in code size as well as run time overhead. An algorithm and its application to assist the compiler in eliminating the redundant bank switching codes introduced and deciding the optimum data allocation to banked memory is presented in this work. A relation matrix formed for the memory bank state transition corresponding to each bank selection instruction is used for the detection of redundant codes. Data allocation to memory is done by considering all possible permutation of memory banks and combination of data. The compiler output corresponding to each data mapping scheme is subjected to a static machine code analysis which identifies the one with minimum number of bank switching codes. Even though the method is compiler independent, the algorithm utilizes certain architectural features of the target processor. A prototype based on PIC 16F87X microcontrollers is described. This method scales well into larger number of memory blocks and other architectures so that high performance compilers can integrate this technique for efficient code generation. The technique is illustrated with an example

Entwurf und Betrieb von Regelungs- und Monitoringsystemen für dezentrale Energiesysteme auf der Basis von verteilten Embedded Systems

Nach einem einleitenden ersten Kapitel wird im zweiten Kapitel der Stand der Technik für Regelungs- und Monitoringsysteme mit vernetzten Systemen dargestellt. Daraus wird die Motivation zur Entwicklung neuer, kostengünstiger Systeme abgeleitet. Im dritten Kapitel folgt eine Darstellung der verschiedenen Arten marktverfügbarer Embedded Systems und dafür geeigneter Betriebs­systeme. Anforderungen an verteilte Regelungssysteme, unterschiedliche Strukturen dieser Systeme und deren Vor- und Nachteile sind Gegenstand des vierten Kapitels. Anhand von Beispielen aus den Bereichen Erzeugungsmanagement für den Betrieb von KWK-Anlagen, Energieverbrauchsmonitoring und Smart-Metering wird der Einsatz von verteilten Regelungs- und Monitoringsystemen im fünften Kapitel dargestellt. Im folgenden sechsten Kapitel wird die Bedeutung normierter Kommunikation für den Einsatz in verteilten Systemen sowie dafür vorhandene Standards aus der elektrischen Energieversorgungstechnik und der Automatisierungstechnik behandelt. Der Stand der Internet-Technik für verteilte Systeme ist Gegenstand des siebten Kapitels. Dabei werden zunächst die verschiedenen drahtlosen und drahtgebundenen Kommunikationsmedien vorgestellt und ihre Eigenschaften und die Rand­bedingungen für ihren Einsatz erörtert. Ebenso werden technische Probleme beim Einsatz der Internet-Technik aufgezeigt und Lösungsmöglichkeiten für diese Probleme dargestellt. Es folgt eine Übersicht von Netzwerkdiensten, die für den Betrieb von verteilten Systemen notwendig sind. Außerdem werden Techniken zur Überwachung von verteilten Systemen behandelt. Kapitel acht zeigt Sicherheitsrisiken bei der Nutzung des Internets auf und bewertet verschiedene Techniken zur Absicherung des Netzwerkverkehrs. Kapitel neun stellt ein Internet-basiertes Client-Server-System zur Online-Visualisierung von Anlagendaten im Webbrowser mit Hilfe von Java-Applets und XML-RPC vor. Die Visualisierung von Anlagendaten auf Mobiltelefonen mit Hilfe des Wireless Application Protocol sowie die dafür notwendige Software und Infrastruktur ist Gegenstand des zehnten Kapitels. Im elften Kapitel wird eine neuartige Software für die Simulation von dezentralen Energiesystemen und deren Regelungs­systemen auf Basis von virtuellen Maschinen, virtuellen Netzwerken und einer thermischen Simulationsumgebung vorgestellt sowie deren Anwendung für die Reglerentwicklung erklärt. Verschiedene Techniken für die Installation von Betriebssystemen und Software für die Embedded Systems eines verteilten Systems werden im Kapitel zwölf untersucht. Im Kapitel 13 werden verschiedene Technologien zur Konfiguration und Parametrierung von Regelungssystemen in der industriellen Prozess- und Fertigungs­automatisierung hinsichtlich ihrer Eignung für dezentrale Energiesysteme analysiert. Anschließend wird eine Software zur Installation und Parametrierung von Monitoringsystemen sowie der dazugehörigen Infrastruktur vorgestellt. Kapitel 14 beschäftigt sich mit Anforderungen an die Hardware für verteilte Systeme und mit Maßnahmen zur Erhöhung der Betriebs- und der Datensicherheit. Im 15. Kapitel werden die in den bisherigen Kapiteln vorgestellten Techniken anhand eines großen verteilten Monitoringsystems und anhand eines Power Flow and Power Quality Management Systems auf Basis von verteilten Embedded Systems evaluiert. Kapitel 16 fasst die Ergebnisse der Arbeit zusammen und enthält einen Ausblick auf zukünftige Entwicklungen.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

HLA-A Typing in formalin-fixed paraffin embedded tissue samples : towards potential retrospective analysis

El Antígeno Leucocitario Humano (HLA en inglés) ha sido descrito en muchos casos como factor de pronóstico para cáncer. La característica principal de los genes de HLA, localizados en el cromosoma 6 (6p21.3), son sus numerosos polimorfismos. Los análisis de secuencia de nucleótidos muestran que la variación está restringida predominantemente a los exones que codifican los dominios de unión a péptidos de la proteína. Por lo tanto, el polimorfismo del HLA define el repertorio de péptidos que se unen a los alotipos de HLA y este hecho define la habilidad de un individuo para responder a la exposición a muchos agentes infecciosos durante su vida. La tipificación de HLA se ha convertido en un análisis importante en clínica. Muestras de tejido embebidas en parafina y fijadas con formalina (FFPE en inglés) son recolectadas rutinariamente en oncología. Este procedimiento podría ser utilizado como una buena fuente de ADN, dado que en estudios en el pasado los ensayos de recolección de ADN no eran normalmente llevados a cabo de casi ningún tejido o muestra en procedimientos clínicos regulares. Teniendo en cuenta que el problema más importante con el ADN de muestras FFPE es la fragmentación, nosotros propusimos un nuevo método para la tipificación del alelo HLA-A desde muestras FFPE basado en las secuencias del exón 2, 3 y 4. Nosotros diseñamos un juego de 12 cebadores: cuatro para el exón 2 de HLA-A, tres para el exón 3 de HLA-A y cinco para el exón 4 de HLA-A, cada uno de acuerdo las secuencias flanqueantes de su respectivo exón y la variación en la secuencia entre diferentes alelos. 17 muestran FFPE colectadas en el Hospital Universitario de Karolinska en Estocolmo Suecia fueron sometidas a PCR y los productos fueron secuenciados. Finalmente todas las secuencias obtenidas fueron analizadas y comparadas con la base de datos del IMGT-HLA. Las muestras FFPE habían sido previamente tipificadas para HLA y los resultados fueron comparados con los de este método. De acuerdo con nuestros resultados, las muestras pudieron ser correctamente secuenciadas. Con este procedimiento, podemos concluir que nuestro estudio es el primer método de tipificación basado en secuencia que permite analizar muestras viejas de ADN de las cuales no se tiene otra fuente. Este estudio abre la posibilidad de desarrollar análisis para establecer nuevas relaciones entre HLA y diferentes enfermedades como el cáncer también.

Synthesis of fused cyclic systems containing medium-sized rings through tandem ROM-RCM of norbornene derivatives embedded in a carbohydrate template

A general approach for the synthesis of fused cyclic systems containing medium-sized rings (7-9) has been developed. The key steps involve a diastereoface-selective Diels-Alder reaction of the dienophiles 4a-d attached to a furanosugar with cyclopentadiene and ring opening (ROM)-ring closing metathesis (RCM) of the resulting norbornene derivatives 10a-d and 11a-d. Diels-Alder reaction of the dienophiles 4a-d with cyclopentadiene in the absence of a catalyst produced 10a-d as the major product arising through addition of the diene to the unhindered Si-face. The most interesting and new aspect of the Diels-Alder reaction of these dienophiles is the accessibility of the Re-face that was blocked by the alkenyl chains under Lewis acid catalysis producing the diastereoisomers 11a-d exclusively. The reversal of facial selectivity from an uncatalyzed reaction to a catalyzed one is unprecedented. The observed stereochemical dichotomy is attributed to rotation of the enone moiety along the or bond linking the sugar moiety during formation of the chelate 13. This makes the Re-face of the enone moiety in 4a-d unhindered. Diels-Alder reaction of the carbocyclic analogue 15 under Lewis acid catalysis produced a 1: 1 mixture of the adducts 16 and 17 confirming the participation of sugar ring oxygen in chelate formation. Finally ROM-RCM of 10a-d and 11a-d with Grubbs' catalyst afforded the cis-syn-cis and cis-anti-cis bicyclo-annulated sugars 21a-d and 23a-d, respectively, containing 7-9 membered rings.

Integrative workflow-embedded support for process automation and management

This paper presents the on-going research performed in order to integrate process automation and process management support in the context of media production. This has been addressed on the basis of a holistic approach to software engineering applied to media production modelling to ensure design correctness, completeness and effectiveness. The focus of the research and development has been to enhance the metadata management throughout the process in a similar fashion to that achieved in Decision Support Systems (DSS) to facilitate well-grounded business decisions. The paper sets out the aims and objectives and the methodology deployed. The paper describes the solution in some detail and sets out some preliminary conclusions and the planned future work.

A parallel convolutional coder including embedded puncturing with application to consumer devices

As consumers demand more functionality) from their electronic devices and manufacturers supply the demand then electrical power and clock requirements tend to increase, however reassessing system architecture can fortunately lead to suitable counter reductions. To maintain low clock rates and therefore reduce electrical power, this paper presents a parallel convolutional coder for the transmit side in many wireless consumer devices. The coder accepts a parallel data input and directly computes punctured convolutional codes without the need for a separate puncturing operation while the coded bits are available at the output of the coder in a parallel fashion. Also as the computation is in parallel then the coder can be clocked at 7 times slower than the conventional shift-register based convolutional coder (using DVB 7/8 rate). The presented coder is directly relevant to the design of modern low-power consumer devices