CMOS integration of AlN based piezoelectric microcantilevers

El gran crecimiento de los sistemas MEMS (Micro Electro Mechanical Systems) así como su presencia en la mayoría de los dispositivos que usamos diariamente despertó nuestro interés. Paralelamente, la tecnología CMOS (Complementary Metal Oxide Semiconductor) es la tecnología más utilizada para la fabricación de circuitos integrados. Además de ventajas relacionadas con el funcionamiento electrónico del dispositivo final, la integración de sistemas MEMS en la tecnología CMOS reduce significantemente los costes de fabricación. Algunos de los dispositivos MEMS con mayor variedad de aplicaciones son los microflejes. Estos dispositivos pueden ser utilizados para la extracción de energía, en microscopios de fuerza atómica o en sensores, como por ejemplo, para biodetección. Los materiales piezoeléctricos más comúnmente utilizados en aplicaciones MEMS se sintetizan a altas temperaturas y por lo tanto no son compatibles con la tecnología CMOS. En nuestro caso hemos usado nitruro de alumino (AlN), que se deposita a temperatura ambiente y es compatible con la tecnología CMOS. Además, es biocompatible, y por tanto podría formar parte de un dispositivo que actúe como biosensor. A lo largo de esta tesis hemos prestado especial atención en desarrollar un proceso de fabricación rápido, reproducible y de bajo coste. Para ello, todos los pasos de fabricación han sido minuciosamente optimizados. Los parámetros de sputtering para depositar el AlN, las distintas técnicas y recetas de ataque, los materiales que actúan como electrodos o las capas sacrificiales para liberar los flejes son algunos de los factores clave estudiados en este trabajo. Una vez que la fabricación de los microflejes de AlN ha sido optimizada, fueron medidos para caracterizar sus propiedades piezoeléctricas y finalmente verificar positivamente su viabilidad como dispositivos piezoeléctricos. ABSTRACT The huge growth of MEMS (Micro Electro Mechanical Systems) as well as their presence in most of our daily used devices aroused our interest on them. At the same time, CMOS (Complementary Metal Oxide Semiconductor) technology is the most popular technology for integrated circuits. In addition to advantages related with the electronics operation of the final device, the integration of MEMS with CMOS technology reduces the manufacturing costs significantly. Some of the MEMS devices with a wider variety of applications are the microcantilevers. These devices can be used for energy harvesting, in an atomic force microscopes or as sensors, as for example, for biodetection. Most of the piezoelectric materials used for these MEMS applications are synthesized at high temperature and consequently are not compatible with CMOS technology. In our case we have used aluminum nitride (AlN), which is deposited at room temperature and hence fully compatible with CMOS technology. Otherwise, it is biocompatible and and can be used to compose a biosensing device. During this thesis work we have specially focused our attention in developing a high throughput, reproducible and low cost fabrication process. All the manufacturing process steps of have been thoroughly optimized in order to achieve this goal. Sputtering parameters to synthesize AlN, different techniques and etching recipes, electrode material and sacrificial layers are some of the key factors studied in this work to develop the manufacturing process. Once the AlN microcantilevers fabrication was optimized, they were measured to characterize their piezoelectric properties and to successfully check their viability as piezoelectric devices.

Noise and PSRR improvement technique for TPC readout front-end in CMOS. technology.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.

Relevance of porosity and surface chemistry of superactivated carbons in capacitors

We show, through some examples, that chemical activation by alkaline hydroxides permits the preparation of activated carbons with tailored pore volume, pore size distribution, pore structure and surface chemistry, which are useful for their application as electrodes in supercapacitors. Examples are presented discussing the importance of each of these properties on the double layer capacitance, on the kinetics of the electric double-layer charge-discharge process and on the pseudo-capacitative contribution from the surface functional groups or the addition of a conducting polymer.

Asymmetric hybrid capacitors based on activated carbon and activated carbon fibre–PANI electrodes

Composites consisting of polyaniline (PANI) coatings inside the microporosity of an activated carbon fibre (ACF) were prepared by electrochemical and chemical methods. Electrochemical characterization of both composites points out that the electrodes with polyaniline show a higher capacitance than the pristine porous carbon electrode. These materials have been used to develop an asymmetric capacitor based on activated carbon (AC) as negative electrode and an ACF–PANI composite as positive electrode in H2SO4 solution as electrolyte. The presence of a thin layer of polyaniline inside the porosity of the activated carbon fibres avoids the oxidation of the carbon material and the oxygen evolution reaction is produced at more positive potentials. This capacitor was tested in a maximum cell voltage of 1.6 V and exhibited high energy densities, calculated for the unpackaged active materials, with values of 20 W h kg−1 and power densities of 2.1 kW kg−1 with excellent cycle lifetime (90% during the first 1000 cycles) and high coulombic efficiency.

Design of hybrid asymmetric capacitors in aqueous electrolyte using ZTC and ultraporous activated carbons

The use of two different materials as electrodes allows the construction of asymmetric and hybrid capacitors cells with enhanced energy and power density. This approach is especially well-suited for overcoming the limitations of pseudocapacitive materials that provide a huge capacitance boost, but in a limited potential window. In this work, we introduce the concepts and protocols that are required for a successful design of such systems, which is illustrated by the construction of an asymmetric hybrid cell where a zeolite-templated carbon and an ultraporous activated carbon have been combined.

Design of Activated Carbon/Activated Carbon Asymmetric Capacitors

Supercapacitors are energy storage devices that offer a high power density and a low energy density in comparison with batteries. Their limited energy density can be overcome by using asymmetric configuration in mass electrodes, where each electrode works within their maximum available potential window, rendering the maximum voltage output of the system. Such asymmetric capacitors are optimized using the capacitance and the potential stability limits of the electrodes, with the reliability of the design largely depending on the accuracy and the approach taken for the electrochemical characterization. Therefore, the performance could be lower than expected and even the system could break down, if a well thought out procedure is not followed. In this work, a procedure for the development of asymmetric supercapacitors based on activated carbons is detailed. Three activated carbon materials with different textural properties and surface chemistry have been systematically characterized in neutral aqueous electrolyte. The asymmetric configuration of the masses of both electrodes in the supercapacitor has allowed to cover a higher potential window, resulting in an increase of the energy density of the three devices studied when compared with the symmetric systems, and an improved cycle life.

Regulador linear de tensão em tecnologia HV-CMOS

Atualmente, assiste-se na nossa sociedade a um recurso e uso massivo de equipamentos eletrónicos portáteis. Este facto, aliado à competitividade de mercado, exigiu o desenvolvimento desses equipamentos com o intuito de melhorar a sua gestão de potência e, obter, consequentemente, maior autonomia e rendimento. Assim, na gestão de potência de um SoC são os reguladores de tensão que assumem um papel de extrema importância. O trabalho realizado ao longo da presente dissertação pressupõe o projeto de um regulador linear de tensão do tipo LDO em tecnologia HV-CMOS, capaz de suportar tensões de entrada de 12V com vista à alimentação de blocos funcionais RF-CMOS com 3,3V e uma corrente de 100mA. Foi implementado através do processo CMOS de 0.35μm de 50V da Austria Micro Systems. A corrente de quiescente do regulador linear de tensão que determina a eficiência de corrente é de 120,22μA. Possui uma eficiência de corrente de 99,88% e um rendimento de 82,46% quando a tensão mínima de entrada é utilizada. O regulador linear de tensão possui uma tensão de dropout de 707mV. A estabilidade do sistema é mantida mesmo com transições de carga de 10μA para 100mA. O regulador possui um tempo de estabelecimento inferior a 2,4μs e uma variação da tensão de saída relativamente ao seu valor nominal inferior a 18mV, ambos para o pior caso. Porém, este regulador possui um undershoot e um overshoot de +- 1,85V.

A study of some low frequency applications of silicon capacitors. Internal research.

Mode of access: Internet.

Defects in PN junctions and MOS capacitors observed using thermally stimulated current and capacitance measurements, videotape script /

Includes bibliographical references (p. 14).

Radiation effects in metal-oxide-semiconductor capacitors

An investigation has been undertaken into the effects of various radiations on commercially made Al-SiO2-Si Capacitors (MOSCs). Detailed studies of the electrical and physical nature of such devices have been used to characterise both virgin and irradiated devices. In particular, an investigation of the nature and causes of dielectric breakdown in MOSCs has revealed that intrinsic breakdown is a two-stage process dominated by charge injection in a pre-breakdown stage; this is associated with localised high-field injection of carriers from the semiconductor substrate to interfacial and bulk charge traps which, it is proposed, leads to the formation of conducting channels through the dielectric with breakdown occurring as a result of the dissipation of the conduction band energy. A study of radiation-induced dielectric breakdown has revealed the possibility of anomalous hot-electron injection to an excess of bulk oxide traps in the ionization channel produced by very heavily ionizing radiation, which leads to intrinsic breakdown in high-field stressed devices. These findings are interpreted in terms of a modification to the model for radiation-induced dielectric breakdown based upon the primary dependence of breakdown on charge injection rather than high-field mechanisms. The results of a detailed investigation of charge trapping and interface state generation in such MOSCs due to various radiations has revealed evidence of neutron induced interface states, and of the generation of positive oxide charge in devices due to all of the radiations tested. In particular, the greater the linear energy transfer of the radiation, the greater the magnitude of charge trapped in the oxide and the greater the number of interface states generated. These findings are interpreted in terms of Si-H and Si-OH bond-breaking at the Si-SiO2 interface which is enhanced by charge carrier transfer to the interface and by anomalous charge injection to compensate for the excess of charge carriers created by the radiation.

New modular structure DC-DC converter without electrolytic capacitors for renewable energy applications

Electrolytic capacitors are extensively used in power converters but they are bulky, unreliable, and have short lifetimes. This paper proposes a new capacitor-free high step-up dc-dc converter design for renewable energy applications such as photovoltaics (PVs) and fuel cells. The primary side of the converter includes three interleaved inductors, three main switches, and an active clamp circuit. As a result, the input current ripple is greatly reduced, eliminating the necessity for an input capacitor. In addition, zero voltage switching (ZVS) is achieved during switching transitions for all active switches, so that switching losses can be greatly reduced. Furthermore, a three-phase modular structure and six pulse rectifiers are employed to reduce the output voltage ripple. Since magnetic energy stored in the leakage inductance is recovered, the reverse-recovery issue of the diodes is effectively solved. The proposed converter is justified by simulation and experimental tests on a 1-kW prototype.

Especificações e concepções de front-end UHF integrado e multipadrão em tecnologia CMOS 130nm

The Brazilian Environmental Data Collecting System (SBCDA) collects and broadcasts meteorological and environmental data, to be handled by dozens of institutions and organizations. The system space segment, composed by the data collecting satellites, plays an important role for the system operation. To ensure the continuity and quality of these services, efforts are being made to the development of new satellite architectures. Aiming a reduction of size and power consumption, the design of an integrated circuit containing a receiver front-end is proposed, to be embedded in the next SBCDA satellite generations. The circuit will also operate under the requirements of the international data collecting standard ARGOS. This work focuses on the design of an UHF low noise amplifier and mixers in a CMOS standard technology. The specifi- cations are firstly described and the circuit topologies presented. Then the circuit conception is discussed and the design variables derived. Finally, the layout is designed and the final results are commented. The chip will be fabricated in a 130 nm technology from ST Microelectronics.

Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.