Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Five-level inverter voltage-space phasor generation for an open-end winding induction motor drive

A topology for voltage-space phasor generation equivalent to a five-level inverter for an open-end winding induction motor is presented. The open-end winding induction motor is fed from both ends by two three-level inverters. The three-level inverters are realised by cascading two two-level inverters. This inverter scheme does not experience neutral-point fluctuations. Of the two three-level inverters only one will be switching at any instant in the lower speed ranges. In the multilevel carrier-based SPWM used for the proposed drive, a progressive discrete DC bias depending on the speed range is given to the reference wave to reduce the inverter switchings. The drive is implemented and tested with a 1 HP open-end winding induction motor and experimental results are presented.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Analysis of current voltage characteristics of MWIR homojunction photodiodes for uncooled operation

Dark currents n(+)/v/p(+) Hg0.69Cd0.Te-31 mid wave infrared photodiodes were measured at room temperature. The diodes exhibited negative differential resistance at room-temperature, but with increasing leakage currents as a function of reverse bias. The current-voltage characteristics were simulated and fitted by incorporating trap assisted tunneling via traps and Shockley-Read-Hall generation recombination process due to dislocations in the carrier transport equations. The thermal suppression of carriers was simulated by taking energy level of trap (E-t), trap density (N-t) and the doping concentrations of n(+) and v regions as fitting parameters. Values of E-t and N-t were 0.78E(g) and similar to 6-9 x 10(14) cm(-3) respectively for most of the diodes. Variable temperature current voltage measurements on variable area diode array (VADA) structures confirmed the fact that variation in zero bias resistance area product (R(0)A) is related to g-r processes originating from variation in concentration and kind of defects that intersect a junction area. (C) 2012 Elsevier B.V. All rights reserved.

AIM-Spice Integration of a Recursive Model for Threshold Voltage Shift in Thin Film Transistors

Non-crystalline semiconductor based thin film transistors are the building blocks of large area electronic systems. These devices experience a threshold voltage shift with time due to prolonged gate bias stress. In this paper we integrate a recursive model for threshold voltage shift with the open source BSIM4V4 model of AIM-Spice. This creates a tool for circuit simulation for TFTs. We demonstrate the integrity of the model using several test cases including display driver circuits.

Effects of superimposed pulse bias on TiN coating in cathodic arc deposition

Orthogonal designs are used to investigate the main factors when doing experiments in which pulse bias is superimposed on d.c. bias during cathodic are deposition of TiN. Pulse peak, duty cycle, frequency, direct voltage, are current and pressure all are investigated when coating TiN on HSS substrates. Roughness, surface micrograph, microhardness and thickness are tested. By analysis of variance, it is shown that pressure and frequency are the main factors. R-a and droplet density of the film with (d.c. + pulse) bias decrease. A simple explanation for the result is suggested.

Metastability mechanisms in thin film transistors quantitatively resolved using post-stress relaxation of threshold voltage

A new approach is presented to resolve bias-induced metastability mechanisms in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). The post stress relaxation of threshold voltage (V(T)) was employed to quantitatively distinguish between the charge trapping process in gate dielectric and defect state creation in active layer of transistor. The kinetics of the charge de-trapping from the SiN traps is analytically modeled and a Gaussian distribution of gap states is extracted for the SiN. Indeed, the relaxation in V(T) is in good agreement with the theory underlying the kinetics of charge de-trapping from gate dielectric. For the TFTs used in this work, the charge trapping in the SiN gate dielectric is shown to be the dominant metastability mechanism even at bias stress levels as low as 10 V.

Light-bias induced instability and persistent photoconductivity in In-Zn-O/Ga-In-Zn-O thin film transistors

Stress/recovery measurements demonstrate that even high-performance passivated In-Zn-O/ Ga-In-Zn-O thin film transistors with excellent in-dark stability suffer from light-bias induced threshold voltage shift (ΔV T) and defect density changes. Visible light stress leads to ionisation of oxygen vacancy sites, causing persistent photoconductivity. This makes the material act as though it was n-doped, always causing a negative threshold voltage shift under strong illumination, regardless of the magnitude and polarity of the gate bias.

P-16: Light-bias induced instability and persistent photoconductivity in in-zn-o/ga-in-zn-o thin film transistors

Stress/recovery measurements demonstrate that even highperformance passivated In-Zn-O/ Ga-In-Zn-O thin film transistors with excellent in-dark stability suffer from light-bias induced threshold voltage shift (ΔV T) and defect density changes. Visible light stress leads to ionisation of oxygen vacancy sites, causing persistent photoconductivity. This makes the material act as though it was n-doped, always causing a negative threshold voltage shift under strong illumination, regardless of the magnitude and polarity of the gate bias. © 2011 SID.

Probing deep level centers in GaN epilayers with variable-frequency capacitance-voltage characteristics of Au/GaN Schottky contacts

Under identical preparation conditions, Au/GaN Schottky contacts were prepared on two kinds of GaN epilayers with significantly different background electron concentrations and mobility as well as yellow emission intensities. Current-voltage (I-V) and variable-frequency capacitance-voltage (C-V) characteristics show that the Schottky contacts on the GaN epilayer with a higher background carrier concentration and strong yellow emission exhibit anomalous reverse-bias I-V and C-V characteristics. This is attributed to the presence of deep level centers. Theoretical simulation of the low-frequency C-V curves leads to a determination of the density and energy level position of the deep centers. (c) 2006 American Institute of Physics.

Capacitance-voltage characteristic as a trace of the exciton evolvement from spatially direct to indirect in quantum wells

We have investigated the photo-excited capacitance-voltage (C-V) characteristics as well as the photoluminescence spectra under different biases of a wide quantum well (QW) embedded in an n(+)-i-n(+) double-barrier structure. The pronounced peak feature at zero bias in the C-V spectrum observed upon illumination is regarded as a kind of quantum capacitance related to the quantum confined Stark effect, originating from the spatial separation of the photo-generated electron and hole gas in the QW. This fact is further demonstrated through the comparison between the C-V curve with the PL intensity versus applied voltage relationship under the same excitation. The results may provide us with a more direct and sensitive means in the detection of the separation and accumulation of both types of free carriers-electrons and holes-in low-dimensional semiconductor structures, especially in a new type of optical memory cell.

A voltage-controlled tunable two-color infrared photodetector using GaAs/AlAs/GaAlAs and GaAs/GaAlAs stacked multiquantum wells

A voltage-controlled tunable two-color infrared detector with photovoltaic (PV) and photoconductive (PC) dual-mode operation at 3-5 mu m and 8-14 mu m using GaAs/AlAs/AlGaAs double barrier quantum wells (DBQWs) and bound-to-continuum GaAs/AlGaAs quantum wells is demonstrated. The photoresponse peak of the photovoltaic GaAs/AlAs/GaAlAs DBQWs is at 5.3 mu m, and that of the photoconductive GaAs/GaAlAs quantum wells is at 9.0 mu m. When the two-color detector is under a zero bias, the spectral response at 5.3 mu m is close to saturate and the peak detectivity at 80 K can reach 1.0X10(11) cmHz(1/2)/W, while the spectral photoresponsivity at 9.0 mu m is absolutely zero completely. When the external voltage of the two-color detector is changed to 2.0 V, the spectral photoresponsivity at 5.3 mu m becomes zero while the spectral photoresponsivity at 9.0 mu m increases comparable to that at 5.3 mu m under zero bias, and the peak detectivity (9.0 mu m) at 80 K can reach 1.5X10(10) cmHz(1/2)/W. Strictly speaking, this is a real bias-controlled tunable two-color infrared photodetector. We have proposed a model based on the PV and PC dual-mode operation of stacked two-color QWIPs and the effects of tunneling resonance with narrow energy width of photoexcited electrons in DBQWs, which can explain qualitatively the voltage-controlled tunable behavior of the photoresponse of the two-color infrared photodetector. (C) 1996 American Institute of Physics.

Voltage Controlled Intertwined Spiral Arrays for Reconfigurable Metasurfaces

Reconfigurable bistate metasurfaces composed of interwoven spiral arrays with embedded pin diodes are proposed for single and dual polarisation operation. The switching capability is enabled by pin diodes that change the array response between transmission and reflection modes at the specified frequencies. The spiral conductors forming the metasurface also supply the dc bias for controlling pin diodes, thus avoiding the need of additional bias circuitry that can cause parasitic interference and affect the metasurface response. The simulation results show that proposed active metasurfaces exhibit good isolation between transmission and reflection states, while retaining excellent angular and polarisation stability with the large fractional bandwidth (FBW) inherent to the original passive arrays. © 2014 A. Vallecchi et al.

Bias voltagecontrolledphotoluminescencefrom b-In2S3 thin films

b-In2S3 thin filmsweredepositedonIndiumTinOxidesubstratesusingtheChemical SprayPyrolysistechnique.Metalcontactwasdepositedoverthe b-In2S3 thin filmto formahetero-structureofthetypeITO/b-In2S3/Metal.Theintensityoftwophoto- luminescenceemissionsfromthe b-In2S3 thin film,centeredat520and690nmcould be variedbytheapplicationofanexternalbiasvoltagetothishetero-structure.The emissionscouldbeswitchedonoroffdependinguponthemagnitudeoftheexternal appliedbiasvoltage.Thusthepresenceoftwoconductingstatesinthishetero-structure could beidentified.Thetemporalvariationinintensityofthephotoluminescence emissionwiththeapplicationofthebiasvoltagehasalsobeenstudied.Thecondition underwhichphotoluminescencequenchingoccurshasbeenrepresentedbyafirst order differentialequationbetweendiffusionlengthandcarrierconcentration

Low voltage and variable-pressure scanning electron microscopy of fractured composites

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)