Studies on process induced deep levels in silicon

An attempt was made to study the deep level impurities and defects introduced into thyristor grade silicon under different processing conditions. DLTS, C-V and I-V measurements were carried out. The ideality factors of the diodes is around 1-7. Activation energy, trap density and minority carrier lifetime were measured.

The effect of SiC particles on the size and morphology of eutectic silicon in cast A356/SiCp composites

Properties of cast aluminium matrix composites are greatly influenced by the nature of distribution of reinforcing phase in the matrix and matrix microstructural length scales, such as grain size, dendrite arm spacing, size and morphology of secondary matrix phases, etc. Earlier workers have shown that SIC reinforcements can act as heterogeneous nucleation sites for Si during solidification of Al-Si-SiC composites. The present study aims at a quantitative understanding of the effect of SiC reinforcements on secondary matrix phases, namely eutectic Si, during solidification of A356 Al-SiC composites. Effect of volume fraction of SiC particulate on size and shape of eutectic Si has been studied at different cooling rates. Results indicate that an increase in SiC volume fraction leads to a reduction in the size of eutectic Si and also changes its morphology from needle-like to equiaxed. This is attributed to the heterogeneous nucleation of eutectic Si on SiC particles. However, SiC particles are found to have negligible influence on DAS. Under all the solidification conditions studied in the present investigation, SiC particles are found to be rejected by the growing dendrites. (C) 1999 Elsevier Science Ltd. All rights reserved.

Growth mechanism of phases by interdiffusion and atomic mechanism of diffusion in the molybdenum-silicon system

Tracer diffusion coefficients are calculated in different phases in the Mo-Si system from diffusion couple experiments using the data available on thermodynamic parameters. Following, possible atomic diffusion mechanism of the species is discussed based on the crystal structure. Unusual diffusion behaviour is found in the Mo(5)Si(3) and Mo(3)Si phases, which indicate the nature of defects present on different sublattices. Further the growth mechanism of the phases is discussed and morphological evolution during interdiffusion is explained. (C) 2011 Elsevier Ltd. All rights reserved.

Study of formation of silicon carbide in the Acheson process

Formation of silicon carbide in the Acheson process was studied using a mass transfer model which has been developed in this study. The century old Acheson process is still used for the mass production of silicon carbide. A heat resistance furnace is used in the Acheson process which uses sand and petroleum coke as major raw materials.: It is a highly energy intensive process. No mass transfer model is available for this process. Therefore, a mass transfer model has been developed to study the mass transfer aspects of the process along with heat transfer. The reaction kinetics of silicon carbide formation has been taken from the literature. It has been shown that reaction kinetics has a reasonable influence on the process efficiency. The effect of various parameters on the process such as total gas pressure, presence of silicon carbide in the initial charge, etc. has been studied. A graphical user interface has also been developed for the Acheson process to make the computer code user friendly.

Reactive Diffusion Between Vanadium and Silicon

Interdiffusion study is conducted in the V-Si system to determine integrated diffusion coefficients of the phases. Activation energy values are calculated from the experiments conducted at different temperatures. The average values are found to be 208, 240 and 141 kJ/mol, respectively, for the V(3)Si, V(5)Si(3) and VSi(2) phases. The low activation energy for the VSi(2) phase indicates very high concentration of defects or the significant contribution from the grain boundary diffusion. The error in calculation of diffusion parameters from a very thin phase layer in a multiphase diffusion couple is discussed. Further the data available in the literature in this system is compared and the problems in the indirect methodology followed previously to calculate the diffusion parameters are discussed.

Severe wear of a near eutectic aluminium-silicon alloy

The severe wear of a near eutectic aluminium silicon alloy is explored using a range of electron microscopic, spectroscopic and diffraction techniques to identify the residually strained and unstrained regions, microcracks and oxidized regions in the subsurface. In severe wear the contact pressure exceeds the elastic shakedown limit. Under this condition the primary and eutectic silicon particles fragment drastically. The fragments are transported by the matrix as it undergoes incremental straining with each cyclic contact at the asperity level. The grains are refined from similar to 2000 nm in the bulk to 30 nm in the near surface region. A large reduction in the interparticle distance compared with that for a milder stage of wear gives rise to high strain gradients which contribute to an enhancement of the dislocation density. The resulting regions of very high strain in the boundaries of the recrystallized grains as well as within the subgrains lead to the formation of microvoidskracks. This is accompanied by the formation of brittle oxides at these subsurface interfaces due to enhanced diffusion of oxygen. We believe that the abundance of such microcracks in the near surface region, primed by severe plastic deformation, is what distinguishes a severe wear regime from mild wear. (C) 2011 Acta Materialia Inc. Published by Elsevier Ltd. All rights reserved.

Topology Optimization of Micromachined Structures with the Manufacturing Constraints of KOH Etching of (110) Silicon

The focus of this paper is on designing useful compliant micro-mechanisms of high-aspect-ratio which can be microfabricated by the cost-effective wet etching of (110) orientation silicon (Si) wafers. Wet etching of (110) Si imposes constraints on the geometry of the realized mechanisms because it allows only etch-through in the form of slots parallel to the wafer's flat with a certain minimum length. In this paper, we incorporate this constraint in the topology optimization and obtain compliant designs that meet the specifications on the desired motion for given input forces. Using this design technique and wet etching, we show that we can realize high-aspect-ratio compliant micro-mechanisms. For a (110) Si wafer of 250 µm thickness, the minimum length of the etch opening to get a slot is found to be 866 µm. The minimum achievable width of the slot is limited by the resolution of the lithography process and this can be a very small value. This is studied by conducting trials with different mask layouts on a (110) Si wafer. These constraints are taken care of by using a suitable design parameterization rather than by imposing the constraints explicitly. Topology optimization, as is well known, gives designs using only the essential design specifications. In this work, we show that our technique also gives manufacturable mechanism designs along with lithography mask layouts. Some designs obtained are transferred to lithography masks and mechanisms are fabricated on (110) Si wafers.

Studies on the deposition and characterization of silicon oxide films for optical coating applications

Silicon oxide films were deposited by reactive evaporation of SiO. Parameters such as oxygen partial pressure and substrate temperature were varied to get variable and graded index films. Films with a refractive index in the range 1.718 to 1.465 at 550 nm have been successfully deposited. Films deposited using ionized oxygen has the refractive index 1.465 at 550 nm and good UV transmittance like bulk fused quartz. Preparation of graded index films was also investigated by changing the oxygen partial pressure during deposition. A two layer antireflection coating at 1064nm has been designed using both homogeneous and inhomogeneous films and studied their characteristics.

Temperature dependent transport studies in InN quantum dots grown by droplet epitaxy on silicon nitride/Si substrate

InN quantum dots (QDs) were fabricated on silicon nitride/Si (111) substrate by droplet epitaxy. Single-crystalline structure of InN QDs was verified by transmission electron microscopy, and the chemical bonding configurations of InN QDs were examined by x-ray photoelectron spectroscopy. Photoluminescence measurement shows a slight blue shift compared to the bulk InN, arising from size dependent quantum confinement effect. The interdigitated electrode pattern was created and current-voltage (I-V) characteristics of InN QDs were studied in a metal-semiconductor-metal configuration in the temperature range of 80-300K. The I-V characteristics of lateral grown InN QDs were explained by using the trap model. (C) 2011 American Institute of Physics. [doi:10.1063/1.3651762]

“Post silicon debug of SOC designs”

Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.